Pin
No.
Function Name
TYPE
(1)
PULL
(2)
Detail of Function
T4
AXR1[11]/GP5[11]
I/O
IPU
McASP1 serial data
N3
AXR1[10]/GP5[10]
I/O
IPU
M1
AXR1[9]/GP4[9]
I/O
IPD
M2
AXR1[8]/EPWM1A/GP4[8]
I/O
IPD
M3
AXR1[7]/EPWM1B/GP4[7]
I/O
IPD
M4
AXR1[6]/EPWM2A/GP4[6]
I/O
IPD
N1
AXR1[5]/EPWM2B/GP4[5]
I/O
IPD
N2
AXR1[4]/EQEP1B/GP4[4]
I/O
IPD
P1
AXR1[3]/EQEP1A/GP4[3]
I/O
IPD
P2
AXR1[2]/GP4[2]
I/O
IPD
R2
AXR1[1]/GP4[1]
I/O
IPD
T3
AXR1[0]/GP4[0]
I/O
IPD
K2
AHCLKX1/EPWM0B/GP3[14]
I/O
IPD
McASP1 transmit master clock
K3
ACLKX1/EPWM0A/GP3[15]
I/O
IPD
McASP1transmit bit clock
K4
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
I/O
IPD
McASP1 transmit frame sync
L1
AHCLKR1/GP4[11]
I/O
IPD
McASP1 receive master clock
L2
ACLKR1/ECAP2/APWM2/GP4[12]
I/O
IPD
McASP1 receive bit clock
L3
AFSR1/GP4[13]
I/O
IPD
McASP1 receive frame sync
D4
AMUTE1/EPWMTZ/GP4[14]
O
IPD
McASP1 mute output
B8
AXR0[0]/AFSR2/GP3[0]
O
IPD
McASP2 serial data
D8
AXR0[2]/ AXR2[3]/GP3[2]
O
IPD
A7
AXR0[3]/ AXR2[2]/GP3[3]
O
IPD
B7
AXR0[4]/ AXR2[1]/GP3[4]
O
IPD
A5
AXR0[11]/AXR2[0]/GP3[11]
O
IPD
B5
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
O
IPD
McASP2 transmit master clock
C8
AXR0[1]/ ACLKX2/GP3[1]
O
IPD
McASP2 transmit bit clock
C7
AXR0[5]/ AFSX2/GP3[5]
O
IPD
McASP2 transmit frame sync
R12
EMA_CLK/OBSCLK/AHCLKR2/GP1[15]
O
IPU
McASP2 receive master clock
D7
AXR0[6]/ ACLKR2/GP3[6]
I/O
IPD
McASP2 receive bit clock
T7
EMA_CS[3]/AMUTE2/GP2[6]
O
IPU
McASP2 mute output
Universal Serial Bus Module (USB0)
G4
USB0_DM
A
USB0 PHY data minus
F4
USB0_DP
A
USB0 PHY data plus
H5
USB0_VDDA33
PWR
USB0 PHY 3.3-V supply
E3
USB0_VDDA18
PWR
USB0 PHY 1.8-V supply input
C3
USB0_VDDA12 (5)
PWR
USB0 PHY 1.2-V LDO output for bypass cap
D2
USB0_ID
A
USB0 PHY identification (mini-A or mini-B plug)
D3
USB0_VBUS
A
USB0 bus voltage
E4
USB0_DRVVBUS/GP4[15]
O
IPD
USB0 controller VBUS control output
Multiplexed with GPIO bank 4 pin 15
B5
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
I
IPD
USB_REFCLKIN. Optional 48 MHz clock input
Multimedia Card/Secure Digital (MMC/SD)
R9
EMA_A[1]/MMCSD_CLK/UHPI_HCNTL0/GP1[1]
O
IPU
MMCSD_CLK
P9
EMA_A[2]/MMCSD_CMD/UHPI_HCNTL1/GP1[2]
I/O
IPU
MMCSD_CMD
M15
EMA_D[7]/MMCSD_DAT[7]/UHPI_HD[7]/GP0[7]/
I/O
IPU
MMC/SD data
BOOT[13]
N13
EMA_D[6]/MMCSD_DAT[6]/UHPI_HD[6]/GP0[6]
I/O
IPU
N15
EMA_D[5]/MMCSD_DAT[5]/UHPI_HD[5]/GP0[5]
I/O
IPU
P13
EMA_D[4]/MMCSD_DAT[4]/UHPI_HD[4]/GP0[4]
I/O
IPU
P15
EMA_D[3]/MMCSD_DAT[3]/UHPI_HD[3]/GP0[3]
I/O
IPU
R13
EMA_D[2]/MMCSD_DAT[2]/UHPI_HD[2]/GP0[2]
I/O
IPU
R15
EMA_D[1]/MMCSD_DAT[1]/UHPI_HD[1]/GP0[1]
I/O
IPU
T13
EMA_D[0]/MMCSD_DAT[0]/UHPI_HD[0]/GP0[0]/
I/O
IPU
BOOT[12]
General-Purpose IO Only Terminal Functions
K1
GP7[14] (6)
I/O
IPD
General-Purpose IO signal
Reserved and No-connect
F7
RSV1
–
–
Reserved
(Leave unconnected, do not connect to power or ground)
B1
RSV2
PWR
–
Reserved
For proper device operation, this pin must be tied directly to CVDD
H4
NC
–
–
–
F3
NC
–
–
–
C1
NC
–
–
–
C2
NC
–
–
–
96
YSP-CU4300/YSP-CU3300/NS-WSW160
Y
SP-CU430
0/Y
SP-CU330
0/
NS-WSW1
60
DRAFT
