Pin
No.
Port Name
F
u
nction
Name
Terminal
Processing
Processing
Condition
when not
u
sed
Condition when
u
sed
Related Power S
u
pply
OFF
Detail of F
u
nction
Condi-
tion
Proce-
ssing
DIR
Logic
I/O Logic
C2
nCS0
SDRAM_N_
CS0
–
–
O
BUS
SDRAM chip select 0
E3
nWE
SDRAM_N_
WE
–
–
O
BUS
SDRAM write enable
F2
nRAS
SDRAM_N_
RAS
–
–
O
BUS
SDRAM row adddress strobe
E2
nCAS
SDRAM_N_
CAS
–
–
O
BUS
SDRAM col
u
mn address strobe
A9
DQM3
SDRAM_
DQM3
–
–
O
BUS
SDRAM data inp
u
t/o
u
tp
u
t mask3
B9
DQM2
SDRAM_
DQM2
–
–
O
BUS
SDRAM data inp
u
t/o
u
tp
u
t mask2
C9
DQM1
SDRAM_
DQM1
–
–
O
BUS
SDRAM data inp
u
t/o
u
tp
u
t mask1
C10
DQM0
SDRAM_
DQM0
–
–
O
BUS
SDRAM data inp
u
t/o
u
tp
u
t mask0
**
A[12:0]
SDRAM_
A[11:0]
–
–
O
BUS
SDRAM address b
u
s
J2
A13
SDRAM_
BA0
–
–
O
BUS
SDRAM bank select BA0
J1
A14
SDRAM_
BA1
–
–
O
BUS
SDRAM bank select BA1
**
D[31:0]
SDRAM_
DQ[31:0]
–
–
B
BUS
SDRAM data b
u
s
M24 nINT1
–
10kPU
–
–
I
Interr
u
pt
Empty
M23 nINT2
PHY0_N_
INT
10kPU
–
–
I
Interr
u
pt
Interr
u
pt from PHY
AE7 TXD0
DBG_TXD
–
–
O
UART TX
Serial for deb
u
g
AE8 RXD0
DBG_RXD
10kPD
–
–
I
UART RX
Serial for deb
u
g
AD7 AGPIO[4]
DBG_LED0
10kPU
–
–
O
Data
LED for deb
u
g
AD8 AGPIO[1]
DBG_LED1
10kPU
–
–
O
Data
LED for deb
u
g
AC8 AGPIO[2]
NCPU_N_
INT
–
–
O
Data
Interr
u
pt to main microprocessor
AE5 TXD1
NCPU_
MISO
–
–
O
UART TX
Microprocessor comm
u
nication VNP2->R32C
AE6 RXD1
NCPU_
MOSI
10kPD
–
–
I
UART RX
Microprocessor comm
u
nication R32C->VNP2
AD5 AGPIO[10]
–
10kPD
Always
I
–
–
Empty
AD6 AGPIO[7]
–
10kPD
Always
I
–
–
Empty
AC6 AGPIO[8]
PHY01_N_
RST
10kPD
–
–
O
Data
PHY reset
AD4 AGPIO[13]
USB_HIZ
10kPU
–
–
O
Data
Not
u
sed (H: USB disconnected L: USB connected)
AC5 AGPIO[11]
N_WOL
100kPU
–
–
O
Data
No
u
sed (Wake on lan)
AE4 ABPIO[12]
USB_N_
FRONT
10kPD
–
–
O
Data
No
u
sed (H: Rear USBdisconnected L: Front USB)
AC7 AGPIO[5]
–
10kPU
Always
I
–
–
Empty
AE2 AGPIO[18]
–
10kPD
Always
I
–
–
Empty
AE3 RXD2
DOCK_
MISO
10kPD
–
–
I
UART RX
DOCK_ON
UAW_ON
I
iPOD receive data
AD2 AGPIO[19]
–
10kPD
Always
I
–
–
Empty
AD3 AGPIO[16]
–
10kPD
Always
I
–
–
Empty
AD1 AGPIO[20]
PHY0_
N_100M
4.7kPU
–
–
I
Data
H: Ether 10Mbps L: Ether 100Mbps
AC4
PARITY/
AGPIO[14]
PHY0_N_
FDX
4.7kPU
–
–
I
Data
H: Ether half d
u
plex L: Ether f
u
ll d
u
plex
AC3
SIMRST/
AGPIO[17]
PHY0_PD
–
–
O
Data
H: Ether low power L: Ether normal power
AA1 I2C_SDA
EEP_SDA
2.2kPU
–
–
B
Data
I2C EEPROM SDA
Y1
I2C_SCL
EEP_SCL
2.2kPU
–
–
O
Clock
I2C EEPROM SCL
Y3
SPI_SCK
NCPU_
PIC_SCK
–
–
O
Clock
Image data transmission clock
W3
SPI_CS0
DSP2_N_
CS2
10kPD
–
–
O
Data
No
u
sed (DSP2 SPI chip select)
87
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT
Summary of Contents for HTR-8063
Page 25: ...25 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 MEMO DRAFT ...
Page 180: ... ADVANCED SETUP RX V1067 HTR 8063 RX A1000 181 DRAFT ...
Page 181: ...RX V1067 HTR 8063 RX A1000 182 DRAFT ...
Page 182: ...RX V1067 HTR 8063 RX A1000 183 DRAFT ...
Page 183: ... 本機の設定を変更する RX V1067 HTR 8063 RX A1000 184 DRAFT ...
Page 184: ...185 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 DRAFT ...
Page 185: ...RX V1067 HTR 8063 RX A1000 DRAFT ...