Pin
No.
Port Name
Use
Port
Function
Name
Terminal
Processing
Related Power Supply
Detail of Function
OFF
ON
I/O Logic I/O Logic
89
D17/CLK6/
P12_1
CLK6
FPGA_SCL
HDMI_PON
O
Low
O
Clk
FPGA clock (at Boot)
90
D16/TXD6/
SDA6/SRXD6/
P12_0
TXD6
FPGA_
MOSI
HDMI_PON
O
Low
O
Data FPGA transmission data (at Boot)
91 VCC
VCC
VCC
---
92
A8/[A8/D8]/
TA0OUT/UD0A/
UD1A/P3_0
A8
A[8]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
93 VSS
VSS
VSS
---
94
A7/[A7/D7]/
AN2_7/P2_7
A7
A[7]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
95
A6/[A6/D6]/
AN2_6/P2_6
A6
A[6]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
96
A5/[A5/D5]/
AN2_5/P2_5
A5
A[5]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
97
A4/[A4/D4]/
AN2_4/P2_4
A4
A[4]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
98
A3/[A3/D3]/
AN2_3/P2_3
A3
A[3]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
99
A2/[A2/D2]/
AN2_2/P2_2
A2
A[2]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
100
A1/[A1/D1]/BC2/
[BC2/D1]/AN2_1/
P2_1
A1
A[1]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
101
A0/[A0/D0]/BC0/
[BC0/D0]/AN2_0/
P2_0
A0
A[0]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
102
D15/INT5/
IIO0_7/IIO1_7/
P1_7
D15
D[15]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
103
D14/INT4/
IIO0_6/IIO1_6/
P1_6
D14
D[14]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
104
D13/INT3/
IIO0_5/IIO1_5/
P1_5
D13
D[13]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
105
D12/IIO0_4/
IIO1_4/P1_4
D12
D[12]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
106
D11/IIO0_3/
IIO1_3/P1_3
D11
D[11]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
107
D10/IIO0_2/
IIO1_2/P1_2
D10
D[10]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
108
D9/IIO0_1/
IIO1_1/P1_1
D9
D[9]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
109
IIO0_0/IIO1_0/
D8/P1_0
D8
D[8]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
110 AN0_7/D7/P0_7
D7
D[7]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
111 AN0_6/D6/P0_6
D6
D[6]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
112 AN0_5/D5/P0_5
D5
D[5]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
113 AN0_4/D4/P0_4
D4
D[4]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
114 WR3/BC3/P11_4
P11_4 EEP_N_CS
10kPU
AC
O
Low
O
L act EEPROM chip select
115
IIO1_3/RTS8/
CTS8/WR2/CS3/
P11_3
CS3
FPGA_N_
CS
HDMI_PON
O
Low
B
B
u
s
External b
u
s
116
IIO1_2/RXD8/
CS2/P11_2
RXD8
EEP_MISO
AC
O
Low
I
Data FL/Expansion IO/EEPROM reception data
117
IIO1_1/CLK8/
CS1/P11_1
CLK8
EX_CLK
FL/expansion,
s
u
ction
prevention
AC
O
Low
O
Clk
FL/Expansion IO/EEPROM comm
u
nication clock
118
IIO1_0/TXD8/
CS0/P11_0
TXD8
EX_MOSI
FL/expansion,
s
u
ction
prevention
AC
O
Low
O
Data FL/Expansion IO/EEPROM transmission data
119 AN0_3/D3/P0_3
D3
D[3]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
120 AN0_2/D2/P0_2
D2
D[2]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
121 AN0_1/D1/P0_1
D1
D[1]
100kPD
HDMI_PON
I
---
B
B
u
s
External b
u
s
82
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT
Summary of Contents for HTR-8063
Page 25: ...25 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 MEMO DRAFT ...
Page 180: ... ADVANCED SETUP RX V1067 HTR 8063 RX A1000 181 DRAFT ...
Page 181: ...RX V1067 HTR 8063 RX A1000 182 DRAFT ...
Page 182: ...RX V1067 HTR 8063 RX A1000 183 DRAFT ...
Page 183: ... 本機の設定を変更する RX V1067 HTR 8063 RX A1000 184 DRAFT ...
Page 184: ...185 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 DRAFT ...
Page 185: ...RX V1067 HTR 8063 RX A1000 DRAFT ...