Pin
No.
Port Name
Use
Port
Function
Name
Terminal
Processing
Related Power Supply
Detail of Function
OFF
ON
I/O Logic I/O Logic
1
SRXD4/SDA4/
TXD4/ANEX1/
P9_6
TXD4
HDR_MOSI
3.3kPU
PRY
O
Low
O
Data HD Radio or DAB transmission data
(U model)
SDA4
TU_SDA
PRY
O
Low
I/O
Data T
u
ner I2C data
(C, R, T, K, A, B, G, F, L, J models)
2
CLK4/ANEX0/
P9_5
P9_5
VOL1_CLK
PRY
O
Low
O
Clock Vol
u
me/ZoneTone/Selector-1 comm
u
nication clock
3
SS4/RTS4/
CTS4/TB4IN/
DA1/P9_4
P9_4
VOL_MOSI
PRY
O
Low
O
Data Vol
u
me/ZoneTone/Selector-1 and 2 comm
u
nication data
4
SS3/RTS3/
CTS3/TB3IN/
DA0/P9_3
DA0
AMP_LMT
PRY
I
---
O
D/A
Limiter control
5
IEOUT/ISTXD2/
OUTC2_0/
SRXD3/SDA3/
TXD3/TB2IN/
P9_2
SDA3
HDMI_SDA
V encoder
s
u
ction
prevention
HDMI_PON
O
Low
I/O
Data HDMI and AVIDEO 400k I2C data
6
IEIN/ISRXD2/
STXD3/SCL3/
RXD3/TB1IN/
P9_1
SCL3
HDMI_SCL
V encoder
s
u
ction
prevention
HDMI_PON
O
Low
O
Clock HDMI and AVIDEO 400k I2C clock
7
CLK3/TB0IN/
P9_0
P9_0
TU_N_ST
47kPU
PRY
O
Low
I
L act T
u
ner Stereo detection
8
INT8/P14_6
INT8
HRX_N_
INT
HDMI_PON
O
Low
I
L act HDMI RX interr
u
pt
9
INT7/P14_5
INT7
HDMI_
MUTE
HDMI_PON
O
Low
I
H act HDMI m
u
te
10
INT6/P14_4
INT6
ACPWR_
DET
3.3M AC
I
---
I
L act AC power detect
11
P14_3
P14_3 VOL_RB
DSP_PON
I
---
I
Vol
u
me B
12 VDC0
VDC0
VDC0
---
13 P14_1
P14_1 VOL_RA
DSP_PON
I
---
I
Vol
u
me A (Port only for inp
u
t)
14 VDC1
VDC1
VDC1
---
15 NSD
NSD
NSD
4.7kPU
Deb
u
gger
16 CNVSS
CNVSS
DBG_
CNVSS
68kPD
---
17 XCIN/P8_7
P8_7
ISEL_RB
DSP_PON
I
---
I
Inp
u
t selector B
18 XCOUT/P8_6
P8_6
ISEL_RA
DSP_PON
I
---
I
Inp
u
t selector A
19 RESET
RESET
MCPU_N_
RST
10kPU
---
20 XOUT
XOUT XOUT
---
21 VSS
VSS
VSS
---
22 XIN
XIN
XIN
---
23 VCC
VCC
VCC
---
24 NMI/P8_5
NMI
NMI
1kPU
---
25 INT2/P8_4
INT2
WAKEUP_
INT
Odd/even
n
u
mber
detection circ
u
it
AC
O
Low
I
Both
edges
Power switches, MISO interr
u
pt of 232C and DOCK
(Sleep state restored)
26 INT1/P8_3
INT1
REM_IN2
100kPU
AC
O
Low
I
L act Remote control p
u
lse inp
u
t 2 (5V tolerant)
27 INT0/P8_2
INT0
REM_IN1
100kPU
AC
O
Low
I
L act Remote control p
u
lse inp
u
t 1 (5V tolerant)
28
UD0B/UD1B/
IIO1_5/RTS5/
CTS5/SS5/U/
TA4IN/P8_1
P8_1
RWT_
CDDA
DSP_PON
O
Low
O
H act CDDA rewrite path selection
29
UD0A/UD1A/
RXD5/SCL5/
STXD5/U/
TA4OUT/P8_0
RXD5
NCPU_
MISO
NET_PON
O
Low
I
Data Network mod
u
le receive data
30
UD0B/UD1B/
IIO1_4/CLK5/
TA3IN/P7_7
TA3IN
NCPU_N_
INT
NET_PON
O
Low
I
L act Network microprocessor interr
u
pt
31
UD0A/UD1A/
IIO1_3/RTS8/
CTS8/TXD5/
SDA5/SRXD5/
TA3OUT/P7_6
TXD5
NCPU_
MOSI
NET_PON
O
Low
O
Data Network mod
u
le transmission data
79
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT
Summary of Contents for HTR-8063
Page 25: ...25 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 MEMO DRAFT ...
Page 180: ... ADVANCED SETUP RX V1067 HTR 8063 RX A1000 181 DRAFT ...
Page 181: ...RX V1067 HTR 8063 RX A1000 182 DRAFT ...
Page 182: ...RX V1067 HTR 8063 RX A1000 183 DRAFT ...
Page 183: ... 本機の設定を変更する RX V1067 HTR 8063 RX A1000 184 DRAFT ...
Page 184: ...185 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 DRAFT ...
Page 185: ...RX V1067 HTR 8063 RX A1000 DRAFT ...