Pin
No.
Port Name
Use
Port
Function
Name
Terminal
Processing
Related Power Supply
Detail of Function
OFF
ON
I/O Logic I/O Logic
59 VCC
VCC
VCC
---
60
D25/OUTC2_5/
P13_1
P13_1
MT_N_SR_
MI
100kPD
+3.3S_PON
O
Low
O
L act M
u
te S
u
rro
u
nd (Main amp inp
u
t)
61
D24/OUTC2_4/
P13_0
P13_0 MT_N_MZ
100kPD
+3.3S_PON
O
Low
O
L act M
u
te Main Zone (Preo
u
t/Main amp inp
u
t)
62
CLKOUT/BCLK/
R5_3
BCLK
NC(BCLK)
HDMI_PON
O
Low
B
B
u
s
Used by external b
u
s
63 RD/P5_2
RD
MCBUS_N_
RD
HDMI_PON
O
Low
B
B
u
s
External b
u
s
64 WR1/BC1/P5_1
BC1
NC(BC1)
HDMI_PON
O
Low
B
B
u
s
Used by external b
u
s
65 WR0/WR/P5_0
WR
MCBUS_N_
WR
HDMI_PON
I
---
B
B
u
s
External b
u
s
66 D23/P12_7
P12_7
DSP1_N_
CS
DSP_PON
O
Low
O
L act DSP1 chip select
67 D22/P12_6
P12_6
DSP1_N_
SPIRDY
DSP_PON
O
Low
I
L act DSP1 SPI Ready
68 D21/P12_5
P12_5
DIR1_N_
INT
DSP_PON
O
Low
I
L DIR For discrimination of DIR1/DSP1 interr
u
pt
69
CS0/A23/TXD6/
SDA6/SRXD6/
P4_7
CS0
NPGA_N_
CS
HDMI_PON
O
Low
B
B
u
s
External b
u
s
70
CS1/A22/RXD6/
SCL6/STXD6/
P4_6
A22
A[22]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
71
CS2/A21/CLK6/
P4_5
A21
A[21]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
72
CS3/A20/CTS6/
RTS6/SS6/P4_4
A20
A[20]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
73
A19/TXD3/
SDA3/SRXD3/
OUTC2_0/
ISTXD2/IEOUT/
P4_3
A19
A[19]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
74
VCC
VCC
VCC
---
75
A18/RXD3/
SCL3/STXD3/
ISRXD2/IEIN/
P4_2
A18
A[18]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
76 VSS
VSS
VSS
---
77 A17/CLK3/P4_1
A17
A[17]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
78
A16/CTS3/RTS3/
SS3/P4_0
A16
A[16]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
79
A15/[A15/D15]/
TA4IN/U/P3_7
A15
A[15]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
80
A14/[A14/D14]/
TA4OUT/U/P3_6
A14
A[14]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
81
A13/[A13/D13]/
TA2IN/W/P3_5
A13
A[13]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
82
A12/[A12/D12]/
TA2OUT/W/P3_4
A12
A[12]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
83
A11/[A11/D11]/
TA1IN/V/P3_3
A11
A[11]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
84
A10/[A10/D10]/
TA1OUT/V/P3_2
A10
A[10]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
85
A9/[A9/D9]/
TA3OUT/UD0B/
UD1B/P3_1
A9
A[9]
HDMI_PON
O
Low
B
B
u
s
External b
u
s
86 D20/P12_4
P12_4
FPGA_N_
CFG
10kPU
HDMI_PON
O
Low
O
L act FPGA nCONF
87
D19/CTS6/
RTS6/SS6/
P12_3
P12_3
FPGA_N_
STA
10kPU
HDMI_PON
I
---
I
L act FPGA nSTATUS
88
D18/RXD6/
SCL6/STXD6/
P12_2
P12_2
FPGA_
CDONE
10kPU
HDMI_PON
I
---
I
H act FPGA CONF DONE
81
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT
Summary of Contents for HTR-8063
Page 25: ...25 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 MEMO DRAFT ...
Page 180: ... ADVANCED SETUP RX V1067 HTR 8063 RX A1000 181 DRAFT ...
Page 181: ...RX V1067 HTR 8063 RX A1000 182 DRAFT ...
Page 182: ...RX V1067 HTR 8063 RX A1000 183 DRAFT ...
Page 183: ... 本機の設定を変更する RX V1067 HTR 8063 RX A1000 184 DRAFT ...
Page 184: ...185 RX V1067 HTR 8063 RX A1000 RX V1067 HTR 8063 RX A1000 DRAFT ...
Page 185: ...RX V1067 HTR 8063 RX A1000 DRAFT ...
