Yamaha HTR-8063, Service Manual

Page: 86 / 185

Memory
Controller0
Memory
Controller1
SD Host I/F 0
SD Host I/F 1
USB
Encryption
Engine
ARM926EJ-S
ARM9EJ-S MMU
Programmable
DSP
Audio I/F
Audio Engine
Network Engine
802.3
MAC0
802.3
MAC1
Memory I/F
SD Host
I-cache
16KB
D-cache
16KB
JTAG
D-TCM
16KB
DMA
I-TCM
16KB
Dual Timer0
Power Manager
I2C
UART2
UART1
UART0
SPI
GPIO
Clock Gen.
PLL
Reset Control
Dual Timer1
Watchdog
Timer
Interrupt
Controller
IC504: YTD-446CZ (VIDEO P.C.B.)
VNP2 (Video and network processor)
*
No replacement part available. / サービス部品供給なし
Pin
No.
Port Name
F u nction
Name
Terminal
Processing
Processing
Condition
when not u sed
Condition when
u sed
Related Power S u pply
OFF Detail of F u nction
Condi-
tion
Proce-
ssing
DIR Logic I/O Logic
M25 nRESET
VNP2_N_
RST
10kPD – – I L act System reset terminal
T25 XI_S –
5MHz q u artz
crystal u nit
– – I Clock System clock crystal oscillation terminal
T24 XO_S –
5MHz q u artz
crystal u nit
– – O Clock System clock crystal oscillation terminal
AE24 XI_A –
24.576MHz
crystal
oscillator
– – I Clock A u dio clock crystal oscillation terminal
AD24 XO_A – OPEN – – O Clock
T22 TEST0 TEST0 10kPU – – I H act System reset terminal
R23 TEST1 – GND at J – – I H act
T23 TEST2 – GND at J – – I H act
L23 nSCS3 N_SCS3 – – O BUS Chip select 3
L24 nSCS2 N_SCS2 – – O BUS Chip select 2
K23 nSCS1 N_SCS1 – – O BUS Chip select 1 FLASH_N_CS
L24 nSCS0 N_SCS0 – – O BUS Chip select 0
J23 nSLBE N_SLBE – – O BUS Lower byte enable
J24 nSUBE N_SUBE – – O BUS Upper byte enable
K25 nSWR N_SWE – – O BUS Write enable
J25 nSRD N_SRD – – O BUS Read enable
** SA[22:0] SRA[22:0] – – O BUS External I/O address b u s
** SD[15:0] SRD[15:0] 10kPU – – B BUS External I/O data b u s
B1 SCLK0
SDRAM_
CLK0
– – O Clock SDRAM clock enable
C1 SCKE0
SDRAM_
CKE0
– – O H act SDRAM clock enable
D1 SCLK1
SDRAM_
CLK1
– – O Clock SDRAM clock enable
E1 SCKE1
SDRAM_
CKE1
– – O H act SDRAM clock enable
F1 nCS1 – – – O BUS SDRAM chip select 1
86
RX-V1
067/HTR-8063/
RX-A1
0
0
0
RX-V1067/HTR-8063/RX-A1000
DRAFT