CVP-105
13
LSI PIN DESCRIPTION
1
/WRHH
O
HH write
73
D15
I/O
2
PE14
O
Port E
74
D14
I/O
Data bus
3
/WRHL
O
L write
75
D13
I/O
4
CASHH/PA21
I/O
HH Column address strobe/Port A
76
D12
I/O
5
DACK1/PE15
O
DMA transfer strobe/Port E
77
VCC
I
Power supply
6
VSS
I
Ground
78
D11
I/O
Data bus
7
A0
O
79
VSS
I
Ground
8
A1
O
80
D10
I/O
9
A2
O
Address bus
81
D9
I/O
10
A3
O
82
D8
I/O
Data bus
11
A4
O
83
D7
I/O
12
VCC
I
Power supply
84
D6
I/O
13
A5
O
Address bus
85
VCC
I
Power supply
14
VSS
I
Ground
86
D5
I/O
Data bus
15
A6
O
87
VSS
I
Ground
16
A7
O
88
D4
I/O
17
A8
O
89
D3
I/O
18
A9
O
90
D2
I/O
Data bus
19
A10
O
91
D1
I/O
20
A11
O
Address bus
92
D0
I/O
21
A12
O
93
VSS
I
Ground
22
A13
O
94
XTAL
I
Crystal oscillator
23
A14
O
95
MD3
I
Mode select
24
A15
O
96
EXTAL
I
Crystal oscillator
25
A16
O
97
MD2
I
Mode select
26
VCC
I
Power supply
98
NMI
-
Non-maskable interrupt
27
A17
O
Address bus
99
VCC
I
Power supply
28
VSS
I
Ground
100
PA16
I/O
Port A
29
/CASHL/PA20
I/O
HL Column address strobe/Port A
101
PA17
I/O
Port A
30
PA19
I/O
Port A
102
MD1
I
Mode select
31
/RAS/PB2
O
Row address strobe/Port B
103
MD0
I
Mode select
32
/CASL/PB3
O
Column address strobe (low) /Port B
104
PLLVCC
I
PLL Power supply
33
PA18
I/O
Port A
105
PLLCAP
I
PLL capacitor
34
/CASH/PB4
O
Column address strobe (high) /Port B
106
PLLVSS
I
PLL Ground
35
VSS
I
Ground
107
CK/PA15
I/O
Clock/Port A
36
RDWR/PB5
O
DRAM read/write /Port B
108
/RES
I
Reset
37
A18
O
109
TIOC0A/PE0
I/O
MTU input capture/output compare (ch 0)/Port E
38
A19
O
Address bus
110
PE1
I/O
Port E
39
A20
O
111
/DREQ1/PE2
I/O
DMA transfer request/Port E
40
VCC
I
Power supply
112
VCC
I
Power supply
41
A21
O
Address bus
113
PE3
I/O
42
VSS
I
Ground
114
PE4
I/O
Port E
43
/RD
O
Read
115
PE5
I/O
44
/WDTOVF
O
Watch dog timer overflow
116
PE6
I/O
45
D31
I/O
Data bus
117
VSS
I
Ground
46
D30
I/O
Data bus
118
AN0 /PF0
I
47
/WRH
O
High write
119
AN1/ PF1
I
48
/WRL
O
Low write
120
AN2 /PF2
I
49
/CS1
O
Chip select
121
AN3 /PF3
I
Analog input/Port F
50
/CS0
O
Chip select
122
AN4 /PF4
I
51
/IRQ3/PA9
I/O
Interrupt request/Port A
123
AN5/PF5
I
52
/IRQ2/PA8
I/O
Interrupt request/Port A
124
AVSS
I
Analog ground
53
/CS3
O
Chip select
125
AN6/PF6
I
Analog input/ Port F
54
/CS2
O
Chip select
126
AN7/PF7
I
Analog input /Port F
55
VSS
I
Ground
127
AVREF
I
Analog reference voltage
56
D29
I/O
128
AVCC
I
Analog power supply
57
D28
I/O
129
VSS
I
Ground
58
D27
I/O
Data bus
130
RxDO
I
Receive data
59
D26
I/O
131
TxDO
O
Transmit data
60
D25
I/O
132
/IRQ0/ SCK0
I
Interrupt request/Serial clock
61
VSS
I
Ground
133
RxD1
I
Receive data
62
D24
I/O
Data bus
134
TxD1
I/O
SCI
63
VCC
I
Power supply
135
VCC
I
Power supply
64
D23
I/O
136
/IRQ1/SCK1
I
Interrupt request/Serial clock
65
D22
I/O
137
PE7
I/O
66
D21
I/O
138
PE8
I/O
Port E
67
D20
I/O
Data bus
139
PE9
I/O
68
D19
I/O
140
PE10
I/O
69
D18
I/O
141
VSS
I
Ground
70
D17
I/O
142
PE11
I/O
71
VSS
I
Ground
143
PE12
I/O
Port E
72
D16
I/O
Data bus
144
PE13
I/O
HD6437043AF09 (XV664100) CPU
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO.
NAME
I/O
FUNCTION
DM : IC100
H
