Xilinx Zynq UltraScale+ ZCU104, User Manual

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ZCU104 Board User Guide 35
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
The configuration and Quad SPI flash memory section of the Z ynq Ult MPSoC
Technical Reference Manual (UG1085) [Ref 2] provides details on using the memory. For
more Quad SPI details, see the Micron MT25QU512ABB8ESF-0SIT data sheet at the Micron
website [Ref 11] .
USB0 (MIO 52-63)
The USB interface on the PS-side serves multiple roles as a host or device controller. The
USB 3.0 interface is supported by the MPSoC GTR interface while the USB 2.0 capabilities of
the SMSC USB3320C controller are shared on a common USB 3.0 USB type AB connector
(J96).
USB 3.0 Transceiver and USB 2.0 ULPI PHY
[ Figure 2-1 , callout 5]
The ZCU104 board uses a Standard Microsystems Corporation USB3320 USB 2.0 ULPI
transceiver at U116 to support a USB connection to the host computer (see Figure 3-3 ). A
USB cable is supplied in the ZCU104 evaluation kit (standard-A connector to host computer,
micro-B connector to ZCU104 board connector J96). The USB3320 is a high-speed USB 2.0
PHY supporting the UTMI+ low pin interface (ULPI) interface standard. The ULPI standard
defines the interface between the USB controller IP and the PHY device, which drives the
physical USB bus. Use of the ULPI standard reduces the interface pin count between the USB
controller IP and the PHY device.
The USB3320 is clocked by a 24 MHz crystal. See the Standard Microsystems Corporation
(SMSC) USB3320 data sheet for clocking mode details [Ref 12] . The interface to the
USB3320 PHY is implemented through the IP in the XCZU7EV MPSoC PS. The ZCU104
USB3320 PHY supports host only mode. The connections between the USB 2.0 PHY at U116
and the XCZU7EV MPSoC are listed in Table 3-7 .
X-Ref Target - Figure 3-3
Figure 3-3: USB Interface
SM3320
USB2.0
USB
MIO
ULPI
USB3
Connector
USB
GTR
GTR Tx,Rx
X20250-013018
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