Xilinx Zynq UltraScale+ ZCU104, User Manual

Page: 73 / 92

ZCU104 Board User Guide 73
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
U10 MGTREFCLK1P HDMI_DRU_CLOCK_C_N
(1)
48 Q0
8T49N287 U182
U9 MGTREFCLK1N HDMI_DRU_CLOCK_C_P
(1)
47 NQ0
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
Table 3-26: GTH Bank 226 Interface Connections (Cont’d)
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
Table 3-27: GTH Bank 227 Interface Connections
XCZU7EV
(U1) Pin
XCZU7EV Pin
Name
Schematic Net Name
(2)
Connected To
Pin
No.
Pin Name Device
M4 MGTHTXP0 HDMI_TX0_P
(1)
8 IN_D0P
SN64DP159R U94
M3 MGTHTXN0 HDMI_TX0_N
(1)
9 IN_D0N
L6 MGTHTXP1 HDMI_TX1_P
(1)
5 IN_D1P
L5 MGTHTXN1 HDMI_TX1_N
(1)
6 IN_D1N
K4 MGTHTXP2 HDMI_TX2_P
(1)
2 IN_D2P
K3 MGTHTXN2 HDMI_TX2_N
(1)
3 IN_D2N
N2 MGTHRXP0 HDMI_RX0_C_P 29 OUT_D0P
TMDS181IR U19
N1 MGTHRXN0 HDMI_RX0_C_N 28 OUT_D0N
L2 MGTHRXP1 HDMI_RX1_C_P 32 OUT_D1P
L1 MGTHRXN1 HDMI_RX1_C_N 31 OUT_D1N
J2 MGTHRXP2 HDMI_RX2_C_P 35 OUT_D2P
J1 MGTHRXN2 HDMI_RX2_C_N 34 OUT_D2N
H4 MGTHTXP3 FMC_LPC_DP0_C2M_N A34 DP4_C2M_P
FMC LPC J5
H3 MGTHTXN3 FMC_LPC_DP0_C2M_P A35 DP4_C2M_N
G2 MGTHRXP3 FMC_LPC_DP0_M2C_P A14 DP4_M2C_P
G1 MGTHRXN3 FMC_LPC_DP0_M2C_N A15 DP4_M2C_N
T8 MGTREFCLK0P HDMI_8T49N241_OUT_C_N
(1)
22 Q2
8T49N241 U181
T7 MGTREFCLK0N HDMI_8T49N241_OUT_C_P
(1)
23 NQ2
R10 MGTREFCLK1P HDMI_RX_CLK_C_P
(1)
26 OUT_CLKP
TMDS181IR U19
R9 MGTREFCLK1N HDMI_RX_CLK_C_N
(1)
25 OUT_CLKN
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
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