Xilinx Zynq UltraScale+ ZCU104 User Manual Download

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ZCU104 Board User Guide

UG1267 (v1.1) October 9, 2018

www.xilinx.com

Chapter 3:

Board Component Descriptions

PS-Side: GTR Transceivers

[

Figure 2-1

, callout 1]

The PS-side GTR transceiver bank 505 supports two DisplayPort transmit channels, USB (3.0)

and SATA, as shown in

Figure 3-27

X-Ref Target - Figure 3-27

Figure 3-27:

PS-GTR Lane Assignments

X20265-020118

Send Feedback

Summary of Contents for Zynq UltraScale+ ZCU104

Page 1: ...ZCU104 Evaluation Board User Guide UG1267 v1 1 October 9 2018...

Page 2: ...agraphs in PS Side DDR4 Component Memory and PL Side DDR4 SODIMM Socket In Table 3 12 updated GTR_REF_CLK_USB3 frequency to 26 MHz In Table 3 24 replaced LVCMOS12 and LVCMOS18 with LVCMOS33 Appendix B...

Page 3: ...s 15 Jumpers 15 Switches 16 MPSoC Device Configuration 16 JTAG 16 Quad SPI 17 SD 17 Chapter 3 Board Component Descriptions Overview 18 Component Descriptions 18 Zynq UltraScale XCZU7EV MPSoC 18 Encryp...

Page 4: ...nsceivers 74 FPGA Mezzanine Card Interface 76 FMC LPC Connector J5 76 Cooling Fan Connector 79 Switches 80 Board Power System 83 Monitoring Voltage and Current 85 Appendix A VITA 57 1 FMC Connector Pi...

Page 5: ...des application developers an unprecedented level of heterogeneous multiprocessing The ZCU104 evaluation board provides a flexible prototyping platform with high speed DDR4 memory interfaces an FMC ex...

Page 6: ...Diagram PMOD0 1 PL I2C1 HDMI Control GPIO FMC LPC GTH HDMI GTs FMC LPC UART2 UART I2C CAN QSPI SD 3 0 DPAUX 10 100 1000 ENET USB ULPI USB 3 0 GTRs SATA GTRs DisplayPort GTRs PS DDR4 x64 Components Ban...

Page 7: ...SD card Configuration over JTAG with platform cable USB header Configuration over USB to JTAG bridge IDT 8T49N287A clock chip HDMI_DRU_CLOCK PS_REF_CLK GTR_REF_CLK_USB3 GTR_REF_CLK_DP CLK_300 GTR_REF_...

Page 8: ...switches power on off PROG_B boot mode DIP switch Operational status LEDs power status INIT DONE PG DDR power good Power management The ZCU104 provides a rapid prototyping platform for the embedded vi...

Page 9: ...ature Operating 0 C to 45 C Storage 25 C to 60 C Table 1 1 Zynq UltraScale MPSoC ZU7EV Features and Resources Feature Resource Count Quad core Arm Cortex A53 MPCore 1 Dual core Arm Cortex R5 MPCore 1...

Page 10: ...ZCU104 Board User Guide 10 UG1267 v1 1 October 9 2018 www xilinx com Chapter 1 Introduction Humidity 10 to 90 non condensing Operating Voltage 12 VDC Send Feedback...

Page 11: ...ent This document is not intended to be a reference design guide and the information herein should not be used as such Always refer to the schematic layout and XDC files of the specific ZCU104 version...

Page 12: ...ag supplied in your kit If you are returning the adapter to Xilinx Product Support place it back in its antistatic bag immediately X Ref Target Figure 2 1 Figure 2 1 ZCU104 Evaluation Board Components...

Page 13: ...ogramming Options FTDI FT4232HL_64LQFP Hirose ZX62D AB 5P8 21 8 U182 IDT8T49N287 FemtoClock NG Octal Universal Frequency Translator B IDT 8T49N287A 501NLGI 32 9 U98 P12 10 100 1000 MHz Tri Speed Ether...

Page 14: ...onitoring Voltage and Current Sullins PBC36SAAN 1x3 0 1 male pin header 44 29 U181 HDMI Clock Recovery B IDT8T49N241 994NLGI 31 30 SW6 Switches MODE 4 pole DIP 4 pole C K SDA04H1SBD 12 31 U23 I2C1 MIO...

Page 15: ...per Settings Number Ref Des Function Default Schematic Page 33 J85 POR_OVERRIDE 1 2 Enable 2 3 Disable 2 3 3 34 J12 SYSMON I2C address Open SYSMON_VP_R floating 1 2 SYSMON_VP_P pulled down 1 2 3 34 J1...

Page 16: ...to the Zynq UltraScale MPSoC device through the FT4232 Quad USB to multipurpose UART U151 with micro USB connector J164 Table 2 3 Default Switch Settings Number Ref Des Function Default Schematic Page...

Page 17: ...Either power cycle or press the power on reset POR pushbutton SW4 SW4 is callout 20 in Figure 2 1 SD To boot from an SD card 1 Store a valid Zynq UltraScale MPSoC boot image file on to an SD card plu...

Page 18: ...e 2 1 page 13 Component Descriptions Zynq UltraScale XCZU7EV MPSoC Figure 2 1 callout 1 The ZCU104 board is populated with the Zynq UltraScale XCZU7EV 2FFVC1156 MPSoC which combines a powerful process...

Page 19: ...08 0 850 0 892 V For 3E devices PS full power domain supply voltage 0 873 0 900 0 927 V VCC_PSINTLP PS low power domain supply voltage 0 808 0 850 0 892 V For 1LI and 2LE VCCINT 0 72V devices PS low p...

Page 20: ...i 400 MP2 64 KB L2 2 x USB 3 0 NAND x8 ONFI 3 1 2 x SD3 0 eMMC4 51 Quad SPI x 8 2 x SPI 2 x CAN 2 x I2C 2 x UART GPIOs SYSMON MIO Central Switch FPD DMA PCIe Gen4 DisplayPort v1 2 x1 x2 2 x SATA v3 1...

Page 21: ...rface with video resolution up to 4K x 2K 30 300 MHz pixel rate USB 3 0 interface compliant to USB 3 0 specification implementing a 5 Gb s line rate Serial GMII interface supports a 1 Gb s SGMII inter...

Page 22: ...FE rechargeable 1 5V lithium button type battery B1 is soldered to the board with the positive output connected to the XCZU7EV MPSoC U1 VCC_PSBATT pin Y23 The battery supply current IBATT specificatio...

Page 23: ...65 VCC1V2 1 2V DDR4 SODIMM DQ 32 63 PL PL Bank 66 VCC1V2 1 2V DDR4 SODIMM ADDR CTRL PL PL Bank 67 VADJ_FMC 1 1 8V FMC_LPC LA BUS PL Bank 68 VADJ_FMC 1 1 8V FMC_LPC LA BUS PL Bank 87 VCC3V3 3 3V PMOD0...

Page 24: ...Ref 3 The DDR4 0 6V VTT termination voltage is supplied from sink source regulator U178 The connections between the DDR4 memory and the U1 XCZU7EV bank 504 are listed in Table 3 3 Table 3 3 DDR4 Compo...

Page 25: ...AM31 DDR4_DQ12 C2 DQU4 U101 AP31 DDR4_DQ13 C8 DQU5 U101 AN31 DDR4_DQ14 D3 DQU6 U101 AM30 DDR4_DQ15 D7 DQU7 U101 AF25 DDR4_DQ16 G2 DQL0 U99 AG25 DDR4_DQ17 F7 DQL1 U99 AG26 DDR4_DQ18 H3 DQL2 U99 AJ25 D...

Page 26: ...U100 W28 DDR4_DQ46 D3 DQU6 U100 V27 DDR4_DQ47 D7 DQU7 U100 AA32 DDR4_DQ48 G2 DQL0 U2 AA33 DDR4_DQ49 F7 DQL1 U2 AA34 DDR4_DQ50 H3 DQL2 U2 AE34 DDR4_DQ51 H7 DQL3 U2 AD34 DDR4_DQ52 H2 DQL4 U2 AB31 DDR4_D...

Page 27: ...100 AD31 DDR4_DQS4_C F3 DQSL_C U100 Y27 DDR4_DQS5_T B7 DQSU_T U100 Y28 DDR4_DQS5_C A7 DQSU_C U100 AB33 DDR4_DQS6_T G3 DQSL_T U2 AB34 DDR4_DQS6_C F3 DQSL_C U2 W31 DDR4_DQS7_T B7 DQSU_T U2 W32 DDR4_DQS7...

Page 28: ...104 DDR4 PS component interface is a 40 impedance implementations Other memory interface details are also available in the UltraScale Architecture FPGAs Memory Interface Solutions Product Guide PG150...

Page 29: ...ion voltage is supplied from sink source regulator U177 The DDR4 SODIMM socket J1 connections are listed in Table 3 4 Table 3 4 DDR4 SODIMM Socket J1 Connections to FPGA PL Banks 64 65 and 66 XCZU7EV...

Page 30: ...12_DCI 42 DQ11 AB15 DDR4_SODIMM_DQ12 POD12_DCI 24 DQ12 AB16 DDR4_SODIMM_DQ13 POD12_DCI 25 DQ13 AC16 DDR4_SODIMM_DQ14 POD12_DCI 38 DQ14 AC17 DDR4_SODIMM_DQ15 POD12_DCI 37 DQ15 AJ15 DDR4_SODIMM_DQ16 POD...

Page 31: ..._DQ45 POD12_DCI 190 DQ45 AH21 DDR4_SODIMM_DQ46 POD12_DCI 203 DQ46 AG21 DDR4_SODIMM_DQ47 POD12_DCI 204 DQ47 AJ22 DDR4_SODIMM_DQ48 POD12_DCI 216 DQ48 AJ21 DDR4_SODIMM_DQ49 POD12_DCI 215 DQ49 AK20 DDR4_S...

Page 32: ...3_C DIFF_POD12_DCI 74 DQS3_C AA18 DDR4_SODIMM_DQS4_T DIFF_POD12_DCI 179 DQS4_T AB18 DDR4_SODIMM_DQS4_C DIFF_POD12_DCI 177 DQS4_C AF23 DDR4_SODIMM_DQS5_T DIFF_POD12_DCI 200 DQS5_T AG23 DDR4_SODIMM_DQS5...

Page 33: ...77 52 Bank 502 ZU7EV U1 Pin No Schematic Net Name Type MIO25 D29 MIO25_CAN_RX CAN MIO51 F34 MIO51_SDIO_CLK_R SD1 MIO77 L34 MIO77_ENET_MDIO MDIO3 MIO24 E28 MIO24_CAN_TX CAN MIO50 F33 MIO50_SDIO_CMD_R...

Page 34: ...cted NC MIO59 H32 MIO59_USB_DATA3_R USB0 MIO6 A26 Not Connected NC MIO32 B31 Not Connected NC MIO58 H31 MIO58_USB_STP_R USB0 MIO5 D25 MIO5_QSPI_LWR_CS_B QSPI MIO31 B30 NotConnected NC MIO57 H29 MIO57_...

Page 35: ...SB connection to the host computer see Figure 3 3 A USB cable is supplied in the ZCU104 evaluation kit standard A connector to host computer micro B connector to ZCU104 board connector J96 The USB3320...

Page 36: ...2 1 callout 20 Table 3 7 USB 2 0 ULPI Transceiver Connections to XCZU7EV MPSoC XCZU7EV U1 Pin Net Name USB3320 U116 Pin Pin Name U168 4 ULPI0_RST_B 1 27 RESET_B H31 MIO58_USB_STP 2 29 STP G30 MIO53_US...

Page 37: ...cards and peripherals See the SanDisk Corporation Ref 13 or SD Association Ref 14 websites for more information on the SD I O card specification The ZCU104 SD card interface supports the SD1_LS config...

Page 38: ...e connections to the XCZU7EV MPSoC X Ref Target Figure 3 5 Figure 3 5 SD Card Interface X20252 013018 Table 3 8 XCZU7EV MIO Connections to SD Socket via U145 XCZU7EV U1 Pin Net Name J100 SD Card Socke...

Page 39: ...tached FMC card must implement a TDI to TDO connection using a device or bypass jumper to ensure that the JTAG chain connects to the U1 XCZU7EV MPSoC PS M 2 SATA Connector Figure 2 1 callout 32 The M...

Page 40: ...ZCU104 Board User Guide 40 UG1267 v1 1 October 9 2018 www xilinx com Chapter 3 Board Component Descriptions X Ref Target Figure 3 7 Figure 3 7 M 2 Connector U170 X20253 013018 Send Feedback...

Page 41: ...Signal 74 3 3V 72 3 3V 70 3 3V 68 SUSCLK 32 kHz I 0 3 3V ADD_IN CARD KEY M ADD_IN CARD KEY M ADD_IN CARD KEY M ADD_IN CARD KEY M 58 Reserved for MGFG_CLOCK 56 Reserved for MGFG_DATA 54 NC 52 NC 50 NC...

Page 42: ...ND 73 GND 71 GND 69 PEDET GND SATA 67 NC ADD_IN CARD KEY M ADD_IN CARD KEY M ADD_IN CARD KEY M ADD_IN CARD KEY M 57 GND 55 NC 53 NC 51 GND 49 SATA A 47 SATA A 45 GND 43 SATA B 41 SATA B 39 GND 37 NC 3...

Page 43: ...ie offs M 2 Signal Name ZCU104 Tie Off U170 Pin SUSCLK No Connect 68 ALERT No Connect 44 SMB_DATA No Connect 42 SMB_CLK No Connect 40 DEVSLP GND 38 DAS DSS DNP Res to GND 10 PEDET No Connect 69 SATA A...

Page 44: ...EF_CLK_DP 27 MHz Q3 CLK_300_P 300 MHz Q4 GTR_REF_CLK_SATA 125 MHz Q5 CLK_125 125 MHz Q6 Table 3 13 Clock Connections Source to XCZU7EV MPSoC Clock Source Pin Net Name I O Standard XCZU7EV U1 Pin U182...

Page 45: ...nerator IDT8T49N287A 501NLGI Jitter 0 3 ps RMS typical The IDT8T49N287A 501NLGI U182 located on the bottom of the board is a one time programmable clock source with frequency adjustment available over...

Page 46: ...thernet RGMII PHY Ref 16 U98 for Ethernet communications at 10 Mb s 100 Mb s or 1000 Mb s The board supports RGMII mode only The PHY connection to a user provided Ethernet cable is through a Bel Fuse...

Page 47: ...TCA6416A I O expander pin 10 port P06 GEM3_EXP_RESET_B K31 MIO70_ENET_RX_CLK 43 RX_CLK K32 MIO71_ENET_RX_D0 44 RX_DO K33 MIO72_ENET_RX_D1 45 RX_D1 K34 MIO73_ENET_RX_D2 46 RX_D2 L29 MIO74_ENET_RX_D3 47...

Page 48: ...ndicates link established For more Ethernet PHY details see the TI DS83867 data sheet Ref 16 Table 3 15 Ethernet PHY LED Functional Description Pin Type Description Name Number LED_2 61 S I O PD By de...

Page 49: ...l right side yellow LED link established indicator LED_2 is the RJ 45 P12 bezel left side green LED TX RX activity indicator LED_1 is the green DS27 LED mounted on the ZCU104 board top between the dis...

Page 50: ...o 0x20 X Ref Target Figure 3 12 Figure 3 12 I2C1 Bus Topology BANK 500 U1 MIO17 C29 MIO16 A28 PS I2C1 BANK 87 U1 PL I2C1 P12 N12 TCA9548A U34 SC0 SC0 SD1 SC1 SDA SCL L S U136 IIC_EEPROM_SDA SCL 8T49N2...

Page 51: ...EPROM U23 0X34 1 IDT8T49N287 Clock U182 0X7C 2 IRP5401 PMICs PMIC1 0x13 PMIC2 0x14 3 VCC12 INA226 U183 0X40 4 No connection NA 5 FMC LPC J5 0x 6 No connection NA 7 DDR4 SODIMM J1 0x51 Table 3 17 TCA64...

Page 52: ...ugh the single micro AB USB connector J164 Channel A is configured to support the JTAG chain Channel B implements UART0 MIO18 19 connections Channel C implements UART1 MIO20 21 connections Channel D i...

Page 53: ...d through the U151 FT4232HL USB to Quad UART bridge BDBUS port The UART connections from XCZU7EV MPSoC U1 PS side MIO 18 and 19 to the FT4232HL device through level shifter U161 are listed in Table 3...

Page 54: ...5 The PS side CAN bus TX MIO24 U1 pin E28 and RX MIO25 U1 pin D29 signals are routed through TXS0104E level translator U33 and TI SN65HVD232 CAN bus transceiver U122 to the 0 1 inch centered 8 pin mal...

Page 55: ...Gb s 2 70 Gb s or 5 40 Gb s The DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb s data rate which is translated from single ended MIO signals to the differential D...

Page 56: ...ZCU104 Board User Guide 56 UG1267 v1 1 October 9 2018 www xilinx com Chapter 3 Board Component Descriptions X Ref Target Figure 3 15 Figure 3 15 DisplayPort Circuit X16547 013018 Send Feedback...

Page 57: ...GZ device supports the dual mode standard version 1 1 type 1 and type 2 through the digital down converter DDC link or AUX channel The SN65DP159RGZ device supports data rates up to 6 Gb s per data lan...

Page 58: ...escriptions X Ref Target Figure 3 16 Figure 3 16 HDMI Interface Block Diagram 3 6LGH 0 3 0 B 5 9 5 61 3 0 B 0 B 7 B B 9 6 B65 B 7 B 0 B287 6 3520 70 6 7 7HUPLQDWLRQ 1HWZRUN 8 5 0 B 1 0 B287 70 6B 70 6...

Page 59: ...October 9 2018 www xilinx com Chapter 3 Board Component Descriptions X Ref Target Figure 3 17 Figure 3 17 HDMI TX Interface Circuit X16535 020118 X Ref Target Figure 3 18 Figure 3 18 HDMI RX Interfac...

Page 60: ...EN LVCMOS33 42 OE A3 HDMI_TX_CEC LVCMOS33 24 CEC_A TPD12S016RK U70 E3 HDMI_TX_HPD LVCMOS33 3 HPD_A N11 HDMI_SI5324_LOL LVCMOS33 18 LOL SI5319C U108 M12 HDMI_SI5324_RST LVCMOS33 1 RST_B G14 HDMI_REC_CL...

Page 61: ...in free running mode and uses an external oscillator as the reference When the HDMI transmitter is used in pass through mode the 8T49N241 generates a jitter attenuated reference clock to drive the HDM...

Page 62: ...aders J55 right angle female and J87 vertical male The 3 3V PMOD nets are wired to the XCZU7EV device U1 bank 87 Figure 3 20 shows the GPIO PMOD headers J55 and J87 Table 3 23 lists the connections be...

Page 63: ...3 J55 1 H8 PMOD0_1 LVCMOS33 J55 3 G7 PMOD0_2 LVCMOS33 J55 5 H7 PMOD0_3 LVCMOS33 J55 7 G6 PMOD0_4 LVCMOS33 J55 2 H6 PMOD0_5 LVCMOS33 J55 4 J6 PMOD0_6 LVCMOS33 J55 6 J7 PMOD0_7 LVCMOS33 J55 8 J9 PMOD1_0...

Page 64: ...Figure 3 11 page 49 See the Digilent website Ref 20 for more information about the PMOD User I O Figure 2 1 callouts 16 19 The ZCU104 board provides these user and general purpose I O capabilities Fou...

Page 65: ...18 www xilinx com Chapter 3 Board Component Descriptions Figure 3 22 through Figure 3 24 show the GPIO circuits Table 3 24 lists the GPIO connections to XCZU7EV U1 3 3V bank 88 X Ref Target Figure 3 2...

Page 66: ...ZCU104 Board User Guide 66 UG1267 v1 1 October 9 2018 www xilinx com Chapter 3 Board Component Descriptions X Ref Target Figure 3 23 Figure 3 23 GPIO Pushbutton Switches X20262 020118 Send Feedback...

Page 67: ...DS37 2 A5 GPIO_LED_2 LVCMOS33 DS39 2 B5 GPIO_LED_3 LVCMOS33 DS40 2 Directional Pushbuttons Active High B4 GPIO_PB_SW0 LVCMOS33 SW14 3 C4 GPIO_PB_SW1 LVCMOS33 SW15 3 B3 GPIO_PB_SW2 LVCMOS33 SW17 3 C3 G...

Page 68: ...0 MGT1V2_PGOOD Green MGTAVTT VCC_PSPLL 1 2 VDC power on DS21 PL_DDR4_VTERM_0V60_PGOOD Green PL_DDR4_VTERM 0 6 VDC power on DS24 UTIL_2V5 Green UTIL_2V5 2 5 VDC power on DS25 UTIL_3V3_PGOOD Green UTIL_...

Page 69: ...PS_DDR4_VTERM_0V60_PGOOD Green PS_DDR4_VTERM 0 6 VDC power on Notes 1 See the Zynq UltraScale MPSoC Technical Reference Manual UG1085 Ref 2 for more information about Zynq UltraScale MPSoC configurat...

Page 70: ...tivity as listed here Quad 223 MGTREFCLK0 Not connected MGTREFCLK1 Not connected Four GTH transceivers not connected Quad 224 MGTREFCLK0 Not connected MGTREFCLK1 Not connected Four GTH transceivers no...

Page 71: ...MGT_226_2 MGT_226_3 MGT_226_REFCLK_0 MGT_226_REFCLK_1 BANK 224 MGT_224_0 MGT_224_1 MGT_224_2 MGT_224_3 MGT_224_REFCLK_0 MGT_224_REFCLK_1 BANK 227 MGT_227_0 MGT_227_1 MGT_227_2 MGT_227_3 MGT_227_REFCL...

Page 72: ...vers is required Table 3 26 and Table 3 27 list MGTH banks 226 and 227 connections respectively Table 3 26 GTH Bank 226 Interface Connections XCZU7EV U1 Pin XCZU7EV Pin Name Schematic Net Name 2 Conne...

Page 73: ...GTHTXP1 HDMI_TX1_P 1 5 IN_D1P L5 MGTHTXN1 HDMI_TX1_N 1 6 IN_D1N K4 MGTHTXP2 HDMI_TX2_P 1 2 IN_D2P K3 MGTHTXN2 HDMI_TX2_N 1 3 IN_D2N N2 MGTHRXP0 HDMI_RX0_C_P 29 OUT_D0P TMDS181IR U19 N1 MGTHRXN0 HDMI_R...

Page 74: ...rd Component Descriptions PS Side GTR Transceivers Figure 2 1 callout 1 The PS side GTR transceiver bank 505 supports two DisplayPort transmit channels USB 3 0 and SATA as shown in Figure 3 27 X Ref T...

Page 75: ...Interface Connections XCZU7EV U1 Pin XCZU7EV Pin Name Schematic Net Name 2 Connected To Pin No Pin Name Device U29 PS_MGTRTXP0 GT0_DP_TX_P 1 4 ML_LANE1_P DisplayPort connector P11 U30 PS_MGTRTXN0 GT0...

Page 76: ...DP differential pair Two GBTCLK differential clocks 61 ground and 10 power connections The ZCU104 board FMC VADJ voltage for LPC connector J5 is determined by the IRPS5401MTRPBF U180 voltage regulato...

Page 77: ...L15 D12 FMC_LPC_LA05_N LVDS J17 C15 FMC_LPC_LA10_N LVDS K15 D14 FMC_LPC_LA09_P LVDS H16 C18 FMC_LPC_LA14_P LVDS C13 D15 FMC_LPC_LA09_N LVDS G16 C19 FMC_LPC_LA14_N LVDS C12 D17 FMC_LPC_LA13_P LVDS G15...

Page 78: ...H13 FMC_LPC_LA07_P LVDS J16 G16 FMC_LPC_LA12_N LVDS F18 H14 FMC_LPC_LA07_N LVDS J15 G18 FMC_LPC_LA16_P LVDS D17 H16 FMC_LPC_LA11_P LVDS A13 G19 FMC_LPC_LA16_N LVDS C17 H17 FMC_LPC_LA11_N LVDS A12 G21...

Page 79: ...coustically noisy The fan speed PWM versus the FPGA die temperature algorithm along with the over temperature set point and fan failure alarm mechanisms are defined by the strapping resistors on the M...

Page 80: ...out 22 The ZCU104 board power switch is SW1 Sliding the switch actuator from the off to the on position applies 12V power from J52 a 6 pin mini fit connector Green LED DS2 illuminates when the ZCU104...

Page 81: ...the XCZU7EV MPSoC PS_PROG_B pin T24 when pressed see Figure 3 30 This action clears the programmable logic configuration which can then be acted on by the PS software See the Zynq UltraScale MPSoC Tec...

Page 82: ...PS_POR_B goes Low PS_SRST_B Reset Depressing and then releasing pushbutton SW3 causes net PS_SRST_B to strobe Low This reset is used to force a system reset It can be tied or pulled High and can be H...

Page 83: ...8 PHASE_C PHASE_D VCC1V2 7 bit PMBus ADDR 0x43 7 bit I2C ADDR 0x13 Page 47 Power Controller U180 IRPS5401MTRPBF PHASE_A UTIL_3V3 PHASE_B UTIL_1V13 7 bit PMBus ADDR 0x44 7 bit I2C ADDR 0x14 PHASE_C UTI...

Page 84: ...e recommended criteria described in the UltraScale Architecture PCB Design User Guide UG583 Ref 4 Table 3 31 Power System Devices Device Type Ref Des PMBus Addr I2C Addr Description Output Power Rail...

Page 85: ...graphical user interface The onboard Infineon IRPS5401 power controllers listed in Table 3 31 are accessed through the I2C 1x3 male pin connector J175 which is included with the Infineon USB cable Inf...

Page 86: ...f the FPGA mezzanine card FMC low pin count LPC connector defined by the VITA 57 1 FMC specification For a description of how the ZCU104 evaluation board implements the FMC specification see FPGA Mezz...

Page 87: ...board schematic Identify the appropriate pins and replace the net names with net names in the user RTL See the Vivado Design Suite User Guide Using Constraints UG903 Ref 10 for more information The F...

Page 88: ...Electromagnetic Compatibility EMC Directive CE Standards EN standards are maintained by the European Committee for Electrotechnical Standardization CENELEC IEC standards are maintained by the Interna...

Page 89: ...oduct complies with Directive 2002 96 EC on waste electrical and electronic equipment WEEE The affixed product label indicates that the user must not discard this electrical or electronic product in d...

Page 90: ...cuments videos and support resources which you can filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentation and Tutorials O...

Page 91: ...ers User Guide UG576 7 UltraScale Architecture Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide PG156 8 Silicon Labs CP210x USB to UART Installation Guide UG1033 9 Tera Term Terminal Em...

Page 92: ...produce modify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s...

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