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Zynq-7000 PCB Design Guide

www.xilinx.com

2

UG933 (v1.8) November 7,  2014

Revision History

The following table shows the revision history for this document.

 

Date

Version

Revision

06/04/2012

1.0

Initial Xilinx release.

06/06/2012

1.1

Corrected format issue.

08/29/2012

1.2

Updated 

Table 3-1

 and 

Table 3-2

 for additional devices/packages. Added 680 µF 

capacitor specification to 

Table 3-3

.

10/11/2012

1.2.1

Corrected document number (changed UG993 to UG933).

11/05/2012

1.2.2

Corrected sizing problem in PDF (no content change).

02/12/2013

1.3

Added Note 

(2)

 to 

Table 3-2

. Added suggested part numbers to 

Table 3-3

. Modified 

paragraph under 

V

CCPAUX

 – PS Auxiliary Logic Supply

. Modified paragraph under 

V

CCPLL

 – PS PLL Supply

. Added 

Figure 5-3

. Modified second to last sentence and 

added last sentence under 

PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR Reference 

Voltage

. Modified CAUTION! under 

Configuring the V

CCO_MIO0

, V

CCO_MIO1

 Voltage 

Mode

 and Note under 

DDR Supply Voltages

. Changed Cke connection from a 

pull-down resistor to a pull-up resistor in 

Figure 5-5

 through 

Figure 5-7

. Updated 

entire 

MIO/EMIO IP Layout Guidelines

 section. 

04/01/2013

1.4

Added XC7Z100 devices to 

Table 3-1

 and 

Table 3-2

. Updated ESR range values in 

Table 3-3

. Changed “0805 Ceramic Capacitor” section heading to 

Mid and High 

Frequency Capacitors

 and modified first paragraph. Removed dimensions, changed 

“0805” to “0402” in 

Figure 3-1

 and deleted “0402 Ceramic Capacitor” subsection. 

Deleted last sentence under 

, Modes and Attributes

. Changed “minimum” to 

“maximum” in third sentence of second paragraph under 

V

CCPLL

 – PS PLL Supply

. 

Added second to last sentence under 

PS_DDR_VREF0, PS_DDR_VREF1 – PS DDR 

Reference Voltage

. Changed “Rup” to “Rterm” in 

Figure 5-5

 and 

Figure 5-6

. Deleted 

Drst_b from 

Figure 5-6

 and 

Figure 5-7

. Changed Rup pull-up resistor to Rdown 

pull-down resistor in 

Figure 5-7

. Changed LPDDR2 setting in last row of 

Table 5-6

 to 

N/A. Updated values in first row of 

Table 5-9

. Changed “Three” different topologies 

to “two” under 

DDR Routing Topology

. Removed Fly-by topology from 

Figure 5-8

 and 

Table 5-12

. Deleted “NAND (ONFI),” “NOR/Flash/SRAM,” “SPI Master,” “SWDT (System 

Watch Dog Timer),” and “TTC (Triple Time Counter” subsections from 

MIO/EMIO IP 

Layout Guidelines

 and modified remaining subsections. Changed “EN208” to “EN247” 

and “DS821” to “PG054” under 

Additional Resources and Legal Notices in Appendix A

.

09/26/2013

1.5

Added XC7Z010, XC7Z015, and XC7Z030 packages/devices to 

Table 3-1

 and 

Table 3-2

. 

Changed suggested part number for the 4.7 µF capacitor in 

Table 3-3

. Added DDR ECC 

unused pins to 

Table 5-5

. Modified 

Figure 5-6

 (Cke pins are now applied to GND via 

resistor Rdown instead of VTT via Rterm). Expanded first paragraph under 

DDR 

Termination

. Clarified 

DDR Termination

 paragraph. Added fly-by routing to 

DDR 

Routing Topology

 section. Deleted SD/SDIO Peripheral Controller section. Added last 

sentence under sections 

IIC

 and 

SDIO

 and second sentence under 

QSPI

. Added 

Chapter 6, Migration from XC7Z030-SBG485 to XC7Z015-CLG485 Devices

.

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Summary of Contents for Zynq-7000

Page 1: ...Zynq 7000 All Programmable SoC PCB Design Guide UG933 v1 8 November 7 2014...

Page 2: ...0402 Ceramic Capacitor subsection Deleted last sentence under Modes and Attributes Changed minimum to maximum in third sentence of second paragraph under VCCPLL PS PLL Supply Added second to last sen...

Page 3: ...raph under Noise Limits by removing specifications and adding a reference to the data sheet Updated second paragraph under Unconnected VCCO Pins Changed Murata part number from GRM155R60J475ME47D to G...

Page 4: ...n Lines 10 Return Currents 11 Chapter 3 Power Distribution System Introduction 12 PCB Decoupling Capacitors 12 Basic PDS Principles 17 Simulation Methods 31 PDS Measurements 32 Troubleshooting 37 Chap...

Page 5: ...ion from XC7Z030 SBG485 to XC7Z015 CLG485 Devices Introduction 69 Differences between XC7Z030 SBG485 and XC7Z015 CLG485 Devices 69 Appendix A Additional Resources and Legal Notices Xilinx Resources 72...

Page 6: ...ynq 7000 All Programmable SoC PCB Design Guide part of an overall set of documentation on the Zynq 7000 AP SoC is available on the Xilinx website at www xilinx com zynq Additional Support Resources Fo...

Page 7: ...d significantly in the last few decades An insulator substrate material usually FR4 an epoxy glass composite with copper plating on both sides has portions of copper etched away to form conductive pat...

Page 8: ...l and deforming the conductive plating These microvias cannot penetrate more than one or two layers however they can be stacked or stair stepped to form vias traversing the full board thickness Pads a...

Page 9: ...re sizes of current PCB technology define the via arrangement in the area under the device Minimum via diameters and keep out areas around those vias are defined by the PCB manufacturer These diameter...

Page 10: ...Transmission Lines The combination of a signal trace and a reference plane forms a transmission line All I O signals in a PCB system travel through transmission lines For single ended I O interfaces b...

Page 11: ...nes the characteristic impedance of the transmission line formed by the trace and reference plane While interruption of reference plane continuity beneath a trace is not as dramatic in effect as sever...

Page 12: ...AP SoC devices is listed in Table 3 1 and Table 3 2 The optimized quantities of PCB decoupling capacitors assumes that the voltage regulators have stable output voltages and meet the regulator manufac...

Page 13: ...RAM VCCAUX VCCAUX_IO VCCO per Bank 3 4 Bank 0 680 F 330 F 100 F 4 7 F 0 47 F 100 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F or 100 F 4 7 F 0 47 F 47 F CLG225 Z 7010 0 0 1 1 2 NA NA N...

Page 14: ...7 F 100 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F or 100 F 4 7 F 0 47 F 47 F Table 3 2 Required PCB Capacitor Quantities per Device PS Package Device VCCPINT VCCPAUX 1 VCCO_DDR VCCO...

Page 15: ...CB Capacitor Quantities per Device PS Cont d Package Device VCCPINT VCCPAUX 1 VCCO_DDR VCCO_MIO0 VCCO_MIO1 VCCPLL 2 3 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F...

Page 16: ...es PCB Bulk Capacitors Bulk capacitors can be large and sometimes are difficult to place very close to the AP SoC Fortunately this is not a problem because the low frequency energy covered by bulk cap...

Page 17: ...n be placed on both sides of the pads see Figure 3 1D for even lower parasitic inductance but with diminishing returns Basic PDS Principles The purpose of the PDS and the properties of its components...

Page 18: ...g capacitors The first major component of the PDS is the voltage regulator The voltage regulator observes its output voltage and adjusts the amount of current it is supplying to keep the output voltag...

Page 19: ...AP SoC Figure 3 3 shows a simplified PDS circuit with all reactive components represented by a frequency dependent resistor Role of Inductance Inductance is the property of the capacitors and the PCB...

Page 20: ...parasitics in the capacitors and in all PCB current paths It is important that each of these parasitics be minimized Capacitor Parasitic Inductance The capacitance value is often considered to be a ca...

Page 21: ...5 shows a real capacitor s impedance characteristic Overlaid on this plot are curves corresponding to the capacitor s capacitance and parasitic inductance ESL These two curves combine to form the RLC...

Page 22: ...me multiplies the capacitance value This lowers both the high and low frequency impedance at the same time PCB Current Path Inductance The parasitic inductance of current paths in the PCB have three d...

Page 23: ...vias per land is important with ultra low inductance capacitors such as reverse aspect ratio capacitors that place wide terminals on the sides of the capacitor body instead of the ends PCB layout eng...

Page 24: ...determines the pair s spreading inductance The closer the spacing the thinner the dielectric the lower the spreading inductance Approximate values of spreading inductance for different thicknesses of...

Page 25: ...arasitic via inductance in the AP SoC mounting is reduced by keeping the relevant VCC and GND planes as close to the AP SoC as possible close to the top of the PCB stackup Device pinout arrangement de...

Page 26: ...ses the vertical distance VCC and GND via length that currents travel before reaching the associated VCC and GND planes To reduce spreading inductance every VCC plane should have an adjacent GND plane...

Page 27: ...inductance plus the inductance of the vias planes and connecting traces between the capacitor and the AP SoC The capacitor s self resonant frequency FRSELF capacitor data sheet value is much higher th...

Page 28: ...of the curve the capacitors are equally effective Capacitor Anti Resonance One problem associated with combinations of capacitors in a PDS of an AP SoC is anti resonant spikes in the PDS aggregate imp...

Page 29: ...itor s effectiveness For a capacitor to be effective in providing transient current at a certain frequency for example the capacitor s resonant frequency the phase relationship based on the distance t...

Page 30: ...the decoupling capacitors Moving away from the device in concentric rings the termination resistors and transceiver supply filtering should be closest to the device followed by the smallest value dec...

Page 31: ...e without using a fairly sophisticated simulator and taking a significant amount of time Basic lumped RLC simulation is one of the simplest simulation methods Though it does not account for the distri...

Page 32: ...connect directly to the VCC and GND vias with surface traces These capacitors confuse the measurement by acting like a short circuit for the high frequency AC current To make sure the measurements ar...

Page 33: ...ggressor are removed through averaging Power system noise measurements should be made at a few different AP SoC locations to ensure that any local noise phenomena are captured Figure 3 8 shows an aver...

Page 34: ...the oscilloscope however many of these functions do not have resolution sufficient to give a clear picture of the noise spectrum Alternatively a long sequence of time domain data can be captured from...

Page 35: ...A spectrum analyzer takes its measurements using a 50 cable instead of an active probe A good method attaches the measurement cable through a coaxial connector tapped into the power and ground planes...

Page 36: ...zer or an oscilloscope with FFT The power system impedance can be determined either through direct measurement or simulation or a combination of these two as there are often many variables and unknown...

Page 37: ...oise are measured locally at these devices the local PDS and the component decoupling networks should be analyzed Possibility 2 Parasitic Inductance of Planes Vias or Connecting Traces Sometimes the d...

Page 38: ...diodes injecting current into the VCCO PDS If large amounts of noise are present on VCCO the drive strength of these interfaces should be decreased or different termination should be used on input or...

Page 39: ...choose I O interface standards and optimize them according to the purpose of the system This chapter contains the following sections Interface Types Single Ended Signaling Interface Types To better ad...

Page 40: ...Rate SDR and Double Data Rate DDR interfaces has to do with the relationship of the data signals of a bus to the clock signal of that bus In SDR systems data is only registered at the input flip flop...

Page 41: ...er which reduces the need for a large voltage swing of the signal at the input receiver Two 1 8V I O standards that illustrate this are LVCMOS18 and SSTL18 Class 1 The thresholds for 1 8V LVCMOS are s...

Page 42: ...lly refers to impedance matching or impedance compensating devices that are used to maintain signal integrity in an interface While many types of elements can be used as terminators such as resistors...

Page 43: ...utput impedance approximately equal to 50 Figure 4 3 Typically parallel terminations have best performance when VTT the voltage source connected to the parallel termination resistor is equal to half o...

Page 44: ...tion topology Other standards might not have any hard requirements but rather might simply provide examples of termination topologies An example of a standard with specific termination requirements is...

Page 45: ...only applicable termination type for this topography The second critical aspect is the length of the connecting stubs at each receiver These must remain short no more than a fraction of a signal rise...

Page 46: ...are required to assess signal integrity at the individual receivers Table 4 2 lists example I O interface types that can be used with the unidirectional multi drop topography LVTTL and LVCMOS do not s...

Page 47: ...termination Figure 4 8 is rarely appropriate for bidirectional interfaces as incoming signals are attenuated by the series resistor of the receiving transceiver Parallel termination Figure 4 7 almost...

Page 48: ...a driver output impedance of 25 50 parallel terminations are appropriate Figure 4 7 Controlled impedance drivers whether implemented with DCI or with weak LVCMOS drivers should be sized to have an ou...

Page 49: ...vailable it is advisable to use a Thevenin parallel termination Thevenin parallel termination consists of a voltage divider with a parallel resistance equal to the characteristic impedance of the tran...

Page 50: ...vers target to have output impedances close to 40 50 better signal integrity can be achieved without any external source series termination When possible it is a better starting point to consider the...

Page 51: ...logic circuits This supply can be combined with VCCINT if the system does not require the PL supply to be powered down independent of the PS VCCPAUX PS Auxiliary Logic Supply VCCPAUX is a 1 8V nominal...

Page 52: ...ully managed The recommended connection between the 10 F 0603 capacitor and the VCCPLL BGA ball is a planelet with a minimum width of 80 mil 2 mm and a length of less than 3 000 mil 76 mm If a planele...

Page 53: ...ovide a voltage reference for the PS_DDR_DQ and PS_DDR_DQS input receivers They need to be tied to a termination voltage Vtt equal to VCCO_DDR 2 For example for DDR3 VCCO_DDR is set to 1 5V then VREF...

Page 54: ...ll down pull up resistors Unused DDR Memory When no PS DDR memory is used VCCO_DDR should be tied to VCCPAUX PS_DDR_VREF0 1 and PS_DDR_VRN P should be left floating PS MIO Power Supplies VCCO_MIO0 PS...

Page 55: ...used to generate PS_MIO_REF A 0 01 F capacitor shall be added for decoupling If RGMII is not being used PS_MIO_VREF is safe to float Power Sequencing Refer to DS187 Zynq 7000 All Programmable SoC Z 7...

Page 56: ...ignal that is mostly used for debugging proposes PS_SRST_B must be High to begin the boot process If PS_SRST_B is not used it can be pulled High to VCCO_MIO1 Boot Mode Pin MIO 8 MIO 8 is used to confi...

Page 57: ...the recommendations for DDR memory designs for Zynq 7000 AP SoC devices DDR Interface Signal Pins Table 5 4 lists all dynamic memory interface signals in Bank 502 X Ref Target Figure 5 4 Figure 5 4 Se...

Page 58: ...DDR_DQ 31 0 I O Data DDR_DM 3 0 O Data mask DDR_DQS_P 3 0 I O Differential data strobe positive DDR_DQS_N 3 0 I O Differential data strobe negative DDR_VRP I O Used to calibrate input termination DDR...

Page 59: ..._b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VTT...

Page 60: ...ontrl Addr we_b ras_b cas_b cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b cke cke cke cke Addr Command Contrl Addr we_b ras_b cas_b odt cs_...

Page 61: ...y decoupling capacitor is recommended for each IC If a regulator is used a low impedance plane or planelet is recommended for distribution X Ref Target Figure 5 7 Figure 5 7 LPDDR2 Board Implementatio...

Page 62: ...gth All DDR memory devices should be placed as closely to the Zynq 7000 AP SoC device as possible Table 5 8 shows the maximum recommended trace lengths for DDR signals VTT VDDQ 2 VDDQ 2 VDDQ 2 VDDQ 2...

Page 63: ...e the CK trace to be equal to or longer than the DQS trace per byte lane DDR Trace Impedance All DDR signals except DDR_DRST_B require controlled impedance DDR_CKE also requires controlled impedance i...

Page 64: ...20 mm Table 5 12 shows the recommended routing topologies Byte and bit swapping is allowed to facilitate PCB routing except for LPDDR2 which specifically forbids swapping When swapping bits keep all...

Page 65: ...ithout internal delays Requires clock to be delayed using longer PCB routes by 1 5 ns 2 0 ns with respect to average delay of DATA 3 0 and CTL Delay skew for DATA 3 0 and CTL should be less than 100 p...

Page 66: ...en operating the TPIU in MIO mode the trace clock output should be delayed by approximately one half clock period This can be done on the PCB or by the debugging device ARM_DSTREAM Lauterbach Agilent...

Page 67: ...ent of the Zynq 7000 AP SoC device In other words TQSPICKD Tckominflash 2 Tpd requirement For example with a Zynq 7000 AP SoC hold time requirement of 1 3 ns and a flash clock to out of 1 0 ns the pro...

Page 68: ...minimum clock to out time of the Zynq 7000 device Using data from DS191 and a popular flash vendor s data sheet the effect of trace delay on the maximum frequency can be illustrated As can be seen fr...

Page 69: ...e two devices needs to be aware of these differences Differences between XC7Z030 SBG485 and XC7Z015 CLG485 Devices When migrating from an XC7Z030 SBG485 device to an XC7Z015 CLG485 device some key dif...

Page 70: ...argeting maximum performance PCB and system simulations are crucial to determine if system wide timing can be met There are also a number of pinout differences between the two packages as noted in Tab...

Page 71: ...0 SBG485 device Software Considerations The Zynq 7000 XC7Z015 device is not supported in the ISE Design Suite and you should not use the Zynq 7000 XC7Z030 device in the SBG485 package in an attempt to...

Page 72: ...Answer Record to your myAlerts Device User Guides http Zynq 7000 AP SoC Product Page http www xilinx com products silicon devices soc zynq 7000 index htm Xilinx Design Tools Release Notes Installation...

Page 73: ...ics Data Sheet UG865 Zynq 7000 All Programmable SoC Packaging and Pinout Specifications UG821 Zynq 7000 All Programmable SoC Software Developers Guide UG585 Zynq 7000 All Programmable SoC Technical Re...

Page 74: ...ce on the AXI protocol Software Documents UG821 Zynq 7000 All Programmable SoC Software Developers Guide UG873 Zynq 7000 All Programmable SoC Concepts Tools and Techniques CTT The source drivers for s...

Page 75: ...ace standards refer the following documents Note ARM documents can be found at http infocenter arm com help index jsp ARM AMBA Level 2 Cache Controller L2C 310 TRM also called PL310 ARM AMBA Specifica...

Page 76: ...00 Final 070130 SD Association Part E1 SDIO Specification Ver2 00 Final 070130 SD Group Part 1 Physical Layer Specification Ver2 00 Final 060509 Please Read Important Legal Notices The information dis...

Page 77: ...performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos...

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