Zynq-7000 PCB Design Guide
50
UG933 (v1.8) November 7, 2014
Chapter 4:
SelectIO Signaling
LVTTL and LVCMOS do not specify any canonical termination method. Series termination is
not recommended for bidirectional interfaces. Parallel termination and weak drivers,
however, are both appropriate.
LVDCI and HSLVDCI both implicitly use controlled-impedance driver termination.
HSTL Class II specifies parallel termination at both transceivers. The termination voltage V
TT
is defined as half of the supply voltage V
CCO
. The designer can elect either not to use
termination at all or to use a different termination. It is up to the designer to verify through
simulation and measurement that the signal integrity at the receiver is adequate.
The JEDEC specifications for SSTL provide examples of both series termination and parallel
termination. The termination voltage V
TT
is defined as half of the supply voltage V
CCO
.
While the specification document provides examples depicting series termination at the
drivers, it is important to note that the purpose of this is to attempt to match the
impedance of the driver with that of the transmission line. Because the Zynq-7000 AP SoC
SSTL drivers target to have output impedances close to 40–50
Ω
, better signal integrity can
be achieved without any external source-series termination. When possible, it is a better
starting point to consider the use of the 3-state DCI I/O standards (“T_DCI”), which provide
internal parallel termination resistors that are only present when the output buffer is in
3-state. It is up to the designer to carefully choose the I/O standard(s) at the 7 series device,
drive strengths, and on-die termination (ODT) options at the other device(s) in the interface
(usually DRAM ICs) and termination topography though careful simulation and
measurement. See
7 Series FPGAs SelectIO User Guide
for more details on the
available I/O standards and options.
Bidirectional Multi-Point Topographies
In more complex topographies, any transceiver in a multi-point bus can transmit to all other
transceivers. Usually these topographies can only run at very slow clock rates because they
only support very slow signal rise times (10 ns to 50 ns). While useful in some situations, the
drawbacks usually outweigh the benefits. The constraints involved in designing these
topographies with good signal integrity are beyond the scope of this document.
SSTL15 DCI
SSTL18 CLASS II
SSTL18 CLASS II DCI
HSTL CLASS II
HSTL CLASS II DCI
Table 4-3:
Example I/O Interface Types for Bidirectional Point-to-Point I/O Topographies
