Zynq-7000 PCB Design Guide
31
UG933 (v1.8) November 7, 2014
Chapter 3:
Power Distribution System
Unconnected V
CCO
Pins
In some cases, one or more I/O banks in an AP SoC are not used (for example, when an AP
SoC has far more I/O pins than the design requires). In these cases, it might be desirable to
leave the bank’s associated V
CCO
pins unconnected, as it can free up some PCB layout
constraints (less voiding of power and ground planes from via antipads, less obstacles to
signals entering and exiting the pinout array, more copper area available for other planelets
in the otherwise used plane layer).
Leaving the V
CCO
pins of unused I/O banks floating reduces the level of ESD protection on
these pins and the I/O pins in the bank. For maximum ESD protection in an unused bank, all
V
CCO
and I/O pins in that bank should be connected together to the same potential,
whether that be ground, a valid V
CCO
voltage, or a floating plane.
Simulation Methods
Simulation methods, ranging from very simple to very complex, exist to predict the PDS
characteristics. An accurate simulation result is difficult to achieve without using a fairly
sophisticated simulator and taking a significant amount of time.
Basic lumped RLC simulation is one of the simplest simulation methods. Though it does not
account for the distributed behavior of a PDS, it is a useful tool for selecting and verifying
that combinations of decoupling capacitor values will not lead to large anti-resonances.
Lumped RLC simulation is a good method for establishing equivalence of decoupling
networks, such as evaluating an alternative to the capacitors of
.
Lumped RLC simulation is performed either in a version of SPICE or other circuit simulator,
or by using a mathematical tool like MathCAD or Microsoft Excel. Istvan Novak publishes a
free Excel spreadsheet for lumped RLC simulation (among other useful tools for PDS
simulation) on his website under
Tool Download
:
http://www.electrical-integrity.com
also lists a few EDA tool vendors for PDS design and simulation. These tools span
a wide range of sophistication levels.
Table 3-5:
EDA Tools for PDS Design and Simulation
Tool
Vendor
Website URL
ADS
Agilent
SIwave, HFSS
Ansoft
Specctraquest Power Integrity
Cadence
Speed 2000, PowerSI, PowerDC
Sigrity
Hyperlynx PI
Mentor
