Zynq-7000 PCB Design Guide
38
UG933 (v1.8) November 7, 2014
Chapter 3:
Power Distribution System
Other improvements of geometry are via-in-pad (via under the solder land), not shown, and
via-beside-pad (vias straddle the lands instead of being placed at the ends of the lands).
Double vias also improve connecting trace geometry and capacitor land geometry.
Exceptionally thick boards (> 3.2 mm or 127 mils) have vias with higher parasitic
inductance.
To reduce the parasitic inductance, move critical V
CC
/GND plane sandwiches close to the
top surface where the AP SoC is located, and place the capacitors on the top surface where
the AP SoC is located.
Possibility 3: I/O Signals in PCB are Stronger Than Necessary
If noise in the V
CCO
PDS is still too high after refining the PDS, the I/O interface slew rate
and/or drive strength can be reduced. This applies to both outputs from the AP SoC and
inputs to the AP SoC. In severe cases, excessive overshoot on inputs to the AP SoC can
reverse-bias the IOB clamp diodes, injecting current into the V
CCO
PDS.
If large amounts of noise are present on V
CCO
, the drive strength of these interfaces should
be decreased, or different termination should be used (on input or output paths).
Possibility 4: I/O Signal Return Current Traveling in Sub-Optimal Paths
I/O signal return currents can also cause excessive noise in the PDS. For every signal
transmitted by a device into the PCB (and eventually into another device), there is an equal
and opposite current flowing from the PCB into the device's power/ground system. If a
low-impedance return current path is not available, a less optimal, higher impedance path
is used. When I/O signal return currents flow over a less optimal path, voltage changes are
induced in the PDS, and the signal can be corrupted by crosstalk. This can be improved by
ensuring every signal has a closely spaced and fully intact return path.
Methods to correct a sub-optimal return current path:
• Restrict signals to fewer routing layers with verified continuous return current paths.
• Provide low-impedance paths for AC currents to travel between reference planes
(high-frequency decoupling capacitors at PCB locations where layer transitions occur).
