Zynq-7000 PCB Design Guide
22
UG933 (v1.8) November 7, 2014
Chapter 3:
Power Distribution System
As different capacitor values are selected in the same package, the capacitive curve moves
up and down against the fixed inductance curve, as shown in
The low-frequency capacitor impedance can be reduced by increasing the value of the
capacitor; the high-frequency impedance can be reduced by decreasing the inductance of
the capacitor. While it might be possible to specify a higher capacitance value in the fixed
package, it is not possible to lower the inductance of the capacitor (in the fixed package)
without putting more capacitors in parallel. Using multiple capacitors in parallel divides the
parasitic inductance, and at the same time, multiplies the capacitance value. This lowers
both the high and low frequency impedance at the same time.
PCB Current Path Inductance
The parasitic inductance of current paths in the PCB have three distinct sources:
• Capacitor mounting
• PCB power and ground planes
• AP SoC mounting
Capacitor Mounting Inductance
Capacitor mounting refers to the capacitor's solder lands on the PCB, the trace (if any)
between the land and via, and the via.
The vias, traces, and capacitor mounting pads of a 2-terminal capacitor contribute
inductance between 300 pH to 4 nH depending on the specific geometry.
Because the current path’s inductance is proportional to the loop area the current traverses,
it is important to minimize this loop size. The loop consists of the path through one power
X-Ref Target - Figure 3-6
Figure 3-6:
Effective Frequency Example
Inductance (Z)
Frequency
UG933_c3_06_060211
F
2
0805
0805
0.47
μ
F
4.7
μ
F
Inductive
Portion
Z Value at F2 is Equal
