Zynq-7000 PCB Design Guide
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UG933 (v1.8) November 7, 2014
Chapter 3:
Power Distribution System
specially designed capacitor network can accommodate the specific design’s transient
current.
Troubleshooting
In some cases the proper design work is done up-front, but noise problems still exist. This
next section describes possible issues and suggested resolution methods.
Possibility 1: Excessive Noise from Other Devices on the PCB
Sometimes ground and/or power planes are shared among many devices, and noise from
an inadequately decoupled device affects the PDS at other devices. Common causes of this
noise are:
• RAM interfaces with inherently high-transient current demands resulting either from
temporary periodic contention or high-current drivers
• Large ASICs
When unacceptable amounts of noise are measured locally at these devices, the local PDS
and the component decoupling networks should be analyzed.
Possibility 2: Parasitic Inductance of Planes, Vias, or Connecting Traces
Sometimes the decoupling network capacitance is adequate, but there is too much
inductance in the path from the capacitors to the AP SoC.
Possible causes are:
• Wrong decoupling capacitor connecting-trace geometry or solder-land geometry
• The path from the capacitors to the AP SoC is too long
- and/or -
• A current path in the power vias traverses an exceptionally thick PCB stackup
For inadequate connecting trace geometry and capacitor land geometry, review the loop
inductance of the current path. If the vias for a decoupling capacitor are spaced a few
millimeters from the capacitor solder lands on the board, the current loop area is greater
than necessary.
To reduce the current loop area, vias should be placed directly against capacitor solder
lands.
Never
connect vias to the lands with a section of trace.
