Zynq-7000 PCB Design Guide
65
UG933 (v1.8) November 7, 2014
Chapter 5:
Processing System (PS) Power and Signaling
MIO/EMIO IP Layout Guidelines
This section lists MIO/EMIO interface-specific layout guidelines.
CAN (Controller Area Network)
A level shifter must be implemented if using a CAN PHY that operates at 5.0V.
Ethernet GEM
Depending which RGMII specification the external PHY supports, the TX/RX clocks might
need to be delayed on the PCB relative to their respective data and control lines:
• PHYs that support RGMII v1.3
°
Requires clock to be delayed using longer PCB routes by 1.5 ns – 2.0 ns with respect
to average delay of DATA[3:0] and CTL
°
Delay skew for DATA[3:0] and CTL should be less than 100 ps including package
time
• PHYs that support RGMII v2.0 without internal delays
°
Requires clock to be delayed using longer PCB routes by 1.5 ns – 2.0 ns with respect
to average delay of DATA[3:0] and CTL
°
Delay skew for DATA[3:0] and CTL should be less than 100 ps including package
time
• PHYs that support RGMII v2.0 with internal delays (RGMII-ID)
°
Delay skew for DATA[3:0] and CTL to clock delay should be less than ±50 ps
including package time
When using EMIO to connect to the PL, ensure that all clocks (TX and RX) route using
clock-capable I/Os.
IIC
A 4.7 k
Ω
pull-up resistor shall be placed at the far end of the SCL and SDA lines, furthest
from the Zynq-7000 AP SoC device. A level-shifter/repeater might be required depending
on the particular multiplexers used.
PCB and package delay skew for IIC_SDA to IIC_SCL
should be less than ±500 ps.
SDIO
A 40
Ω
–60
Ω
series resistor should be placed on the CLK line, as close to the MIO pin as
possible. A level-shifter might be required depending on the particular voltages used on
