Xilinx T1, User Manual, Page: 9 / 54

Chapter 2
Pin Mapping
This section presents the pin mapping for the Zynq Ult MPSoC and Zynq Ult
RFSoC devices.
Zynq Ult MPSoC ZU19 Pin Map
The following table presents the pin mapping for the Zynq Ult MPSoC ZU19 device.
Table 1: Zynq Ult MPSoC ZU19 Pin Map
Pin Number Signal Name Interface
AM20 BOARD_REV0 Board Rev
AM21 BOARD_REV1 Board Rev
AM22 BOARD_REV2 Board Rev
C14 SFP_HS_PWR_EN Card Power Throttle
P29 NMR Clock Synth Reset
AH23 CLK_GEN_AUX_CS_A0 Clock Synth SDIO Bus
AH20 CLK_GEN_AUX_SCLK Clock Synth SDIO Bus
AJ22 CLK_GEN_AUX_SDI_A1 Clock synth SDIO Bus
AJ21 CLK_GEN_AUX_SDIO Clock synth SDIO Bus
M33 MP_161.13MHZ_MAC_CLK_N Clock: 100G MAC Diff Clock Input (Neg)
M32 MP_161.13MHZ_MAC_CLK_P Clock: 100G MAC Diff Clock Input (Pos)
F28 MP_300MHZ_CLK_DDR_N Clock: DDR4 Diff Clock Input (Neg)
G27 MP_300MHZ_CLK_DDR_P Clock: DDR4 Diff Clock Input (Pos)
AH9 PCIE_MP_REFCLK_N Clock: PCIe Diff Clock (Neg)
AH10 PCIE_MP_REFCLK_P Clock: PCIe Diff Clock (Pos)
AU16 MP_156.25MHZ_CLK1_N Clock: SFP0 & SFP1 Diff Clock1 Input
(Neg)
AU17 MP_156.25MHZ_CLK1_P Clock: SFP0 & SFP1 Diff Clock1 Input
(Pos)
AU18 MP_156.25MHZ_CLK2_N Clock: SFP0 & SFP1 Diff Clock2 Input
(Neg)
AT19 MP_156.25MHZ_CLK2_P Clock: SFP0 & SFP1 Diff Clock2 Input
(Pos)
AK22 AUX_GPIO GPIO - Zynq Ult MPSoC <--
>Clock Synth
Chapter 2: Pin Mapping
UG1495 (v1.0) December 17, 2021 www.xilinx.com
T1 Telco Accelerator Card User Guide 9
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