
DDR4 SDRAM Reference Clocks
Both SoCs require one reference clock for the DDR4 SDRAM memory controller. The reference
clocks for these interfaces are detailed in the following table. Both clocks are 300 MHz by
default.
Table 6: DDR4 SDRAM Reference Clocks
Signal
Target FPGA Input
I/O Standard
P Pin
N Pin
RF_300MHZ_CLK_DDR
IO_L11P/N_T1U_N8_GC
_66
LVDS18
AB7
AB6
MP_300MHZ_CLK_DDR IO_L14P/
N_T2L_N2/3_GC_69
LVDS18
G27
F28
MAC to MAC Interface Reference Clock
Each SoC requires one reference clock for MAC to MAC interface, and both use a 161.1328125
MHz default reference clock.
Table 7: MAC Reference Clocks
Signal
Target FPGA Input
I/O Standard
P Pin
N Pin
RF_161.13MHZ_MAC_C
LK
MGTREFCLK0_129
LVDS18
T28
T29
MP_161.13MHZ_MAC_C
LK
MGTREFCLK0_132
LVDS18
M32
M33
User Clocks
Each SoC has been provided with two user clocks, and both SoCs use a 156.25 MHz default user
clock.
Table 8: User Clocks
Signal
Target FPGA Input
I/O Standard
P Pin
N Pin
RF_156.25MHZ_CLK1
IO_L11P/N_T1U_N8_GC
_65
LVDS18
AK3
AK2
RF_156.25MHZ_CLK2
IO_L12P/N_T1U_N8_GC
_65
LVDS18
AJ3
AJ2
MP_156.25MHZ_CLK1
IO_L11P/N_T1U_N8_GC
_65
LVDS18
AU17
AU16
Chapter 4: Clocking
UG1495 (v1.0) December 17, 2021
T1 Telco Accelerator Card User Guide
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