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• x16 standard card form factor (FHHL), single slot (111.15 mm x 167.65 mm)

• Maintenance port for card maintenance and developer access using the DMB II Interface

(proprietary, requires Xilinx

®

 DMB II kit)

Overview

The system hardware contains a single PCB assembly. The MNC2 card is built with a XCZU21DR
Zynq Ult RFSoC and a XCZU19EG Zynq Ult MPSoC. The connectivity includes
two 25G interfaces and one x16 Gen 3.0 PCIe interface. Each SoC acts as a Gen3.0 x8 endpoint
with respect to root complex. One DDR4 Memory controller is implemented inside the PL
section of both SoCs. A second set of DDR4 memory is interfaced to PS section of both SoCs.
One 100G transceiver is implemented on both SoCs for inter-SoC communication. A detailed
block diagram of the T1 card card is shown in the following figure.

Figure 3: Detailed T1 card Block Diagram

Zync Ult
RFSoC
XCZU21DR

-L2FSVD1156E

Zync Ult

MPSoC

XCZU19EG

-L2FFVD1760E

QSPI Flash 

Memory

Configuration 

Block

IO[0:7]
SCK
CS

DDR4

DDR4_1_A[0:16]
DDR4_1_BA[0:1]
DDR4_1_DM[0:4]
DDR4_1_DQ[0:39]
DDR4_1_A\DQS_T/C[0:4]
DDR4_1_CLK_T/C
DDR4_1_RST

DDR4

DDR4_0_A[0:16]
DDR4_0_BA[0:1]
DDR4_0_DM[0:8]
DDR4_0_DQ[0:71]
DDR4_0_A\DQS_T/C[0:8]
DDR4_0_CLK_T/C
DDR4_0_RST

I2C_0

25G MAC0

GT_RX_P/N
GT_RX_P/N
SFP0_REFCLK_RST

I2C_1

25G MAC1

GT_RX_P/N
GT_RX_P/N
SFP1_REFCLK_RST

JTAG

TCK

TMS

TDI

TDO

UART

100G MAC0

MAC0_CLK_P/N

MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]

MAC0_RST

I2C_0

Clock

Reset

PCIe Hard 

Block Gen3 x8

PCIE_MGT_TX_P/N[0:7]

PCIE_MGT_RX_P/N[0:7]

PCIE_RST

PCIE_REFCLK_P/N

Clock

Buffer

MPSOC

RFSOC

Clock

Synchronizer

Level

Translator

Level

Translator

DDR4, x16

8GB + ECC

DDR4, x16

4GB + ECC

SFP28

SFP28

FTDI
Chip

Mini-USB

Conn

JTAG

TCK
TMS
TDI
TDO

UART

100G MAC0

MAC0_CLK_P/N
MAC0_TX_P/N[0:3]
MAC0_RX_P/N[0:3]
MAC0_RST

I2C_0

Clock

Reset

PCIe Hard 

Block Gen3 x8

PCIE_REFCLK_P/N

PCIE_RST

PCIE_MGT_RX_P/N[0:7]

PCIE_MGT_TX_P/N[0:7]

EEPROM

Clock Generator

I2C Level

Translator

MCU

Outlet Temp 

Sensor

Inlet Temp 

Sensor

I2C_0

I2C_2

I2C_1

PSU

FTDI
Chip

CLOCK

Buffer

Configuration 

Block

IO[0:7]

SCK

CS

DDR4

DDR4_1_A[0:16]
DDR4_1_BA[0:1]

DDR4_1_DM[0:4]

DDR4_1_DQ[0:39]

DDR4_1_A\DQS_T/C[0:4]

DDR4_1_CLK_T/C

DDR4_1_RST

DDR4

DDR4_0_A[0:16]
DDR4_0_BA[0:1]

DDR4_0_DM[0:8]

DDR4_0_DQ[0:71]

DDR4_0_A\DQS_T/C[0:8]

DDR4_0_CLK_T/C

DDR4_0_RST

QSPI Flash 

Memory

DDR4, x16

8GB + ECC

DDR4, x16

4GB + ECC

OR

Module

PM

PCIE EDGE FINGER

PS

PS

VCC_0V72

VCC_0V85

VCC_0V9

VCC_1V2

VCC_1V8

VCC_3V3

VCC_12V

PCIE_12V

ATX_12V

PCIe

 Gen 

3.0

PCIE_REFCLK_P/N

PCIe

 Gen 

3.0

PPS_IN_MPSOC

PPS_IN_RFSOC

PPS_IN

PPS_OUT

25G 

MAC

25G 

MAC

100G MAC

X24621-092320

Chapter 1: Introduction

UG1495 (v1.0) December 17, 2021

 

www.xilinx.com

T1 Telco Accelerator Card User Guide

 6

Send Feedback

Summary of Contents for T1

Page 1: ...ving non inclusive language from our products and related collateral We ve launched an internal initiative to remove language that could exclude people or reinforce historical biases including terms e...

Page 2: ...erence Clock 35 SFP28 Clocks 35 DDR4 SDRAM Reference Clocks 36 MAC to MAC Interface Reference Clock 36 User Clocks 36 Chapter 5 LEDs 38 Chapter 6 Xilinx Design Constraints XDC File 39 Appendix A Progr...

Page 3: ...mation 50 VCCI Class A Statement 51 Appendix C Additional Resources and Legal Notices 52 Xilinx Resources 52 Documentation Navigator and Design Hubs 52 References 53 Revision History 53 Please Read Im...

Page 4: ...Target applications for the T1 card include O RAN fronthaul termination 4G LTE and 5G NR high PHY lookaside acceleration supporting 3GPP split option 7 2x 5G layer 1 L1 high PHY lookaside acceleration...

Page 5: ...coding Dual NOR flash of 2x 256 MB in QSPI mode for Zynq UltraScale MPSoC Dual NOR flash of 2x 256 MB in QSPI mode for Zynq UltraScale RFSoC 4 GB of DDR4 programmable logic PL memory to each Zynq Ult...

Page 6: ..._RX_P N GT_RX_P N SFP0_REFCLK_RST I2C_1 25G MAC1 GT_RX_P N GT_RX_P N SFP1_REFCLK_RST JTAG TCK TMS TDI TDO UART 100G MAC0 MAC0_CLK_P N MAC0_TX_P N 0 3 MAC0_RX_P N 0 3 MAC0_RST I2C_0 Clock Reset PCIe Ha...

Page 7: ...tails Figure 4 Zynq UltraScale MPSoC XCZU19EG Device Zynq UltraScale RFSoC Specification The Zynq UltraScale RFSoC device on the card is a XCZU21DR L2FSVD1156E The L2 speed grade designates this is a...

Page 8: ...Figure 5 Zynq UltraScale RFSoC XCZU21DR Device Chapter 1 Introduction UG1495 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card User Guide 8 Send Feedback...

Page 9: ...21 CLK_GEN_AUX_SDIO Clock synth SDIO Bus M33 MP_161 13MHZ_MAC_CLK_N Clock 100G MAC Diff Clock Input Neg M32 MP_161 13MHZ_MAC_CLK_P Clock 100G MAC Diff Clock Input Pos F28 MP_300MHZ_CLK_DDR_N Clock DDR...

Page 10: ...aScale MPSoC Zynq UltraScale RFSoC PL F15 MPSOC_RFSOC_PL_GPIO7 GPIO Zynq UltraScale MPSoC Zynq UltraScale RFSoC PL F14 MPSOC_RFSOC_PL_GPIO8 GPIO Zynq UltraScale MPSoC Zynq UltraScale RFSoC PL G14 MPSO...

Page 11: ...TEST_LED LED MPSoC General Purpose LED2 AK19 MP_RST_REQ MPSoC SC Reset request A29 CLK_GPIO_0 NOT USED A30 CLK_GPIO_1 NOT USED B29 CLK_GPIO_2 NOT USED B30 CLK_GPIO_3 NOT USED C29 CLK_GPIO_4 NOT USED N...

Page 12: ...PCIe AP6 PCIE_TX7_P PCIe N25 PL_DDR4_2_A0 PL 72 bit DDR4 P26 PL_DDR4_2_A6 PL 72 bit DDR4 E25 PL_DDR4_2_BA1 PL 72 bit DDR4 M28 PL_DDR4_2_BG0 PL 72 bit DDR4 R27 PL_DDR4_2_PAR PL 72 bit DDR4 D25 PL_DDR4...

Page 13: ...DR4_2_DQ5 PL 72 bit DDR4 A26 PL_DDR4_2_DQ6 PL 72 bit DDR4 J24 PL_DDR4_2_DQ14 PL 72 bit DDR4 K23 PL_DDR4_2_DQ8 PL 72 bit DDR4 J22 PL_DDR4_2_DQ13 PL 72 bit DDR4 K22 PL_DDR4_2_DQ10 PL 72 bit DDR4 H22 PL_...

Page 14: ...PL_DDR4_2_DQ40 PL 72 bit DDR4 N16 PL_DDR4_2_DQ43 PL 72 bit DDR4 R18 PL_DDR4_2_DQ45 PL 72 bit DDR4 N19 PL_DDR4_2_DQ46 PL 72 bit DDR4 D20 PL_DDR4_2_DQ48 PL 72 bit DDR4 C22 PL_DDR4_2_DQ49 PL 72 bit DDR4...

Page 15: ...L_DDR4_2_DQS3_N PL 72 bit DDR4 F23 PL_DDR4_2_DQS3_P PL 72 bit DDR4 K16 PL_DDR4_2_DQS8_N PL 72 bit DDR4 K17 PL_DDR4_2_DQS8_P PL 72 bit DDR4 P18 PL_DDR4_2_DQS5_N PL 72 bit DDR4 P19 PL_DDR4_2_DQS5_P PL 7...

Page 16: ...4_2_BG0 PS 36 bit DDR4 AY31 PS_DDR4_2_CAS PS 36 bit DDR4 AY29 PS_DDR4_2_CK_N PS 36 bit DDR4 BA29 PS_DDR4_2_CK_P PS 36 bit DDR4 BA34 PS_DDR4_2_CKE PS 36 bit DDR4 BA33 PS_DDR4_2_CS PS 36 bit DDR4 AY22 P...

Page 17: ...7 PS 36 bit DDR4 AY35 PS_DDR4_2_DQ34 PS 36 bit DDR4 BB38 PS_DDR4_2_DQ39 PS 36 bit DDR4 AW36 PS_DDR4_2_DQ36 PS 36 bit DDR4 AY36 PS_DDR4_2_DQ38 PS 36 bit DDR4 AY37 PS_DDR4_2_DQ32 PS 36 bit DDR4 AV24 PS_...

Page 18: ..._DQ1 QSPI Flash AJ23 MP_QSPI_UPR_DQ2 QSPI Flash AJ24 MP_QSPI_UPR_DQ3 QSPI Flash E15 SOC_INT Zynq UltraScale RFSoC and Zynq UltraScale MPSoC interrupt to SC W29 MP_PS_RST SC Zynq UltraScale MPSoC PS Re...

Page 19: ...k 100G MAC Diff Clock Input Neg T28 RF_161 13MHZ_MAC_CLK_P Clock 100G MAC Diff Clock Input Pos AB6 RF_300MHZ_CLK_DDR_N Clock DDR4 Diff Clock Input Neg AB7 RF_300MHZ_CLK_DDR_P Clock DDR4 Diff Clock Inp...

Page 20: ...UltraScale MPSoC Zynq UltraScale RFSoC PS A19 MPSOC_RFSOC_PS_GPIO3 GPIO Zynq UltraScale MPSoC Zynq UltraScale RFSoC PS A20 MPSOC_RFSOC_PS_GPIO4 GPIO Zynq UltraScale MPSoC Zynq UltraScale RFSoC PS C19...

Page 21: ..._P PCIe D30 PCIE_RX11_N PCIe D29 PCIE_RX11_P PCIe D34 PCIE_RX10_N PCIe D33 PCIE_RX10_P PCIe E32 PCIE_RX9_N PCIe E31 PCIE_RX9_P PCIe F34 PCIE_RX8_N PCIe F33 PCIE_RX8_P PCIe A32 PCIE_RX15_P PCIe A31 PCI...

Page 22: ...1_A11 PL 72 bit DDR4 Y1 PL_DDR4_1_A7 PL 72 bit DDR4 AD2 PL_DDR4_1_PAR PL 72 bit DDR4 Y2 PL_DDR4_1_BG0 PL 72 bit DDR4 AC7 PL_DDR4_1_CS PL 72 bit DDR4 AB4 PL_DDR4_1_A1 PL 72 bit DDR4 AA4 PL_DDR4_1_A3 PL...

Page 23: ...it DDR4 W4 PL_DDR4_1_DQ60 PL 72 bit DDR4 Y6 PL_DDR4_1_DQ62 PL 72 bit DDR4 G7 PL_DDR4_1_DQ26 PL 72 bit DDR4 W8 PL_DDR4_1_DQ57 PL 72 bit DDR4 Y5 PL_DDR4_1_DQ56 PL 72 bit DDR4 D9 PL_DDR4_1_DQ2 PL 72 bit...

Page 24: ...Q51 PL 72 bit DDR4 H15 PL_DDR4_1_DQ71 PL 72 bit DDR4 K18 PL_DDR4_1_DQ64 PL 72 bit DDR4 J17 PL_DDR4_1_DQ67 PL 72 bit DDR4 J15 PL_DDR4_1_DQ69 PL 72 bit DDR4 J19 PL_DDR4_1_DQ66 PL 72 bit DDR4 L15 PL_DDR4...

Page 25: ...t DDR4 AP20 PS_DDR4_1_A1 PS 36 bit DDR4 AL21 PS_DDR4_1_A10 PS 36 bit DDR4 AL19 PS_DDR4_1_A11 PS 36 bit DDR4 AK21 PS_DDR4_1_A12 PS 36 bit DDR4 AK17 PS_DDR4_1_A13 PS 36 bit DDR4 AP18 PS_DDR4_1_A2 PS 36...

Page 26: ...4_1_DQ18 PS 36 bit DDR4 AM8 PS_DDR4_1_DQ3 PS 36 bit DDR4 AH16 PS_DDR4_1_DQ21 PS 36 bit DDR4 AJ13 PS_DDR4_1_DQ16 PS 36 bit DDR4 AL16 PS_DDR4_1_DQ23 PS 36 bit DDR4 AK13 PS_DDR4_1_DQ20 PS 36 bit DDR4 AL1...

Page 27: ...R4_1_DQS4_P PS 36 bit DDR4 AN22 PS_DDR4_1_ODT PS 36 bit DDR4 AG18 PS_DDR4_1_PAR PS 36 bit DDR4 AH17 PS_DDR4_1_RAS PS 36 bit DDR4 AK20 PS_DDR4_1_RF_BG1 PS 36 bit DDR4 AH21 PS_DDR4_1_RST PS 36 bit DDR4...

Page 28: ...Number Production Net Name Interface Description 1 MPSOC_MSP_GPIO1 GPIO Zynq UltraScale MPSoC SC 2 MPSOC_MSP_GPIO2 GPIO Zynq UltraScale MPSoC SC 3 MP_CONFIG_PROG_HS Zynq UltraScale MPSoC Configuration...

Page 29: ...C Board Rev 49 MSP_ADC_A20 ADC for Board Voltage Sense 50 MSP_ADC_A19 ADC for Board Voltage Sense 51 MSP_ADC_A18 ADC for Board Voltage Sense 52 MSP_ADC_A17 ADC for Board Voltage Sense 53 MSP_ADC_A16 A...

Page 30: ...R Power on SC Reset Input 88 MP_CPU_RST_HS Zynq UltraScale MPSoC User Reset Output 89 RF_PS_RST_HS Zynq UltraScale RFSoC PS SRST Reset 90 RF_CPU_RST_HS Zynq UltraScale RFSoC User Reset Output 91 RF_PS...

Page 31: ...used to test during manufacturing Fomerica TAS A1EH1 837 25 Gb s SFP28 dual rate SR transceiver Mellanox MCP2M00 A002E30N Ethernet passive copper cable 25 GbE SFP28 2m 30AWG Maintenance Port for UART...

Page 32: ...es and is automatically recognized by the Xilinx toolchain when a USB connection is present Refer to Appendix A Programming the Devices Using JTAG for further details IEEE 1588 Support The T1 card car...

Page 33: ...RFSoC and Zynq UltraScale MPSoC devices IMPORTANT For these links to be detected it is essential that x8x8 bifurcation be supported in the host server The PCIe form factor is FHHL with the high mass...

Page 34: ...OUT X24622 092320 The Zynq UltraScale MPSoC recovers clock information from IEEE 1588 packets on the SFP ports This clock is fed to an IDT 8A34001 Network Synchronizer which in turn cleans up noise an...

Page 35: ...CIE_REFCLK Table 4 PCIe Reference Clock Signal Target FPGA Input I O Standard P Pin N Pin PCIE_MP_REFCLK MGTREFCLK0_226 HCSL AH10 AH9 PCIE_RF_REFCLK MGTREFCLK0_130 HCSL M28 M29 SFP28 Clocks SFP28 inte...

Page 36: ...face and both use a 161 1328125 MHz default reference clock Table 7 MAC Reference Clocks Signal Target FPGA Input I O Standard P Pin N Pin RF_161 13MHZ_MAC_C LK MGTREFCLK0_129 LVDS18 T28 T29 MP_161 13...

Page 37: ...Signal Target FPGA Input I O Standard P Pin N Pin MP_156 25MHZ_CLK2 IO_L12P N_T1U_N8_GC _65 LVDS18 AT19 AU18 Chapter 4 Clocking UG1495 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card U...

Page 38: ...G_DONE Orange LED On when the Zynq UltraScale RFSoC PL configuration is completed D13 RF_LED Green LED Connected to SoC for workload usage LED is user defined D14 RF_PS_TEST_LED Green LED Connected to...

Page 39: ...card XDC file is available for download from the T Series lounge contact your Xilinx representative for access Note There are production and prototype versions of the XDC Ensure that you have selected...

Page 40: ...JTAG using an ADK connector The Xilinx tools must be installed on a computer and then connected to the T1 card through an ADK connector An ADK connector is not part of the T1 card and must be obtaine...

Page 41: ...DK card then connect the ADK card to a micro USB cable so that it can connect to a computer that can run the Xilinx tools The full connection is shown below Appendix A Programming the Devices Using JT...

Page 42: ...out the back of the server This setup allows the USB to be connected to an external laptop running on the server The Xilinx tools can be on the laptop or the server to program the devices on the T1 c...

Page 43: ...e MPSoC QSPI Using SDK The following describes using the how to use the Xilinx tools to program the QSPIs on the T1 card Note If you use this method the Xilinx tools must be loaded on the server and i...

Page 44: ...Program Flash wizard browse to and select the boot bin image file that was created for the Zynq UltraScale MPSoC 6 Select the auto detect option in the target device Zynq UltraScale MPSoC will be sele...

Page 45: ...ADK connected is shown in the previous section outside of a server 2 In Xilinx SDK create a new hardware project using the Zynq UltraScale RFSoC HDF file 3 In Xilinx SDK select Xilinx Tools Program F...

Page 46: ...grammed directly using the Vivado Design Suite Make sure you have installed Vivado before proceeding with the steps below IMPORTANT When you install Vivado and then perform a cold boot of the servers...

Page 47: ...host machine Flashing the Images Using the Program Flash Application The Zynq UltraScale MPSoC and Zynq UltraScale RFSoC can be programmed using the Program Flash application part of the Vivado Desig...

Page 48: ...00477 4 jsn Alveo DMBv2 FT4232H 50771B2161A9AA 147e1093 0 name xczu21dr idcode 147e1093 5 jsn Alveo DMBv2 FT4232H 50771B2161A9AA 5ba00477 1 name arm_dap idcode 5ba00477 3 Program the image See the fol...

Page 49: ...afety The following safety standards apply to all products listed in this document IEC 62368 1 2nd Edition 2014 A11 2017 Information technology equipment Safety Part 1 General requirements EN 62368 1...

Page 50: ...and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC rules These limits are designed to provide reasonable protection against harmful interference when the e...

Page 51: ...VCCI Class A Statement Appendix B Regulatory Compliance Statements UG1495 v1 0 December 17 2021 www xilinx com T1 Telco Accelerator Card User Guide 51 Send Feedback...

Page 52: ...Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx Design Hubs provide links to documentation organized by design tasks and other topics whic...

Page 53: ...ES OF MERCHANTABILITY NON INFRINGEMENT OR FITNESS FOR ANY PARTICULAR PURPOSE and 2 Xilinx shall not be liable whether in contract or tort including negligence or under any other theory of liability fo...

Page 54: ...L OF A VEHICLE SAFETY APPLICATION UNLESS THERE IS A SAFETY CONCEPT OR REDUNDANCY FEATURE CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD SAFETY DESIGN CUSTOMER SHALL PRIOR TO USING OR DISTRIB...

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