Xilinx T1, User Manual, Page: 35 / 54

The Network Synchronizer device generates the other clocks on the card, including the reference
clocks for the DDR4 SDRAM interfaces, user logic, and the MAC-to-MAC communication
between the programmable logic and the I/O interfaces. The clock frequencies are factory
programmed, and as such are the default on power-up.
PCIe Reference Clock
The 16 lanes from the PCIe card edge are connected to the Zynq Ult MPSoC (GTH
quads 226 and 227) and the Zynq Ult RFSoC (GTY quads 130 and 131). Among 16 lanes,
x8 are fed to the Zynq Ult MPSoC and x8 to the Zynq Ult RFSoC. The PCIe
subsystem uses a 100 MHz clock (
PCIE_REFCLK
).
Table 4: PCIe Reference Clock
Signal Target FPGA Input I/O Standard P Pin N Pin
PCIE_MP_REFCLK MGTREFCLK0_226 HCSL AH10 AH9
PCIE_RF_REFCLK MGTREFCLK0_130 HCSL M28 M29
SFP28 Clocks
SFP28 interfaces are in GTY quads 133 and 134. Both use a 161.1328125 MHz default
reference clock. It also recovers clocks from the incoming packets.
The clock outputs are AC coupled with 0.01 uF capacitors. LVDS standard is followed, as shown
in the following table.
Table 5: SFP28 Clocks
Signal Target FPGA Input I/O Standard P Pin N Pin
SFP0_IN_CLK MGTREFCLK0_133 LVDS18 F32 F33
SFP0_161.13MHZ_CLK MGTREFCLK0_133 LVDS18 H32 H33
SFP1_IN_CLK MGTREFCLK0_134 LVDS18 B32 B33
SFP1_161.13MHZ_CLK MGTREFCLK0_134 LVDS18 D32 D33
Chapter 4: Clocking
UG1495 (v1.0) December 17, 2021 www.xilinx.com
T1 Telco Accelerator Card User Guide 35
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