Programming
4-7
Note: The 6300ESB allows multiple PCI bus Interrupts to be mapped to one AT-bus interrupt.
Example: In the BIOS setup menu map the VMEbus IRQ(1) to PCI IRQ(11).
VMEbus Interrupt Generation
The XVME 689-VR7 can generate VMEbus interrupts on all 7 levels. There is a unique STATUS/ID
associated with each level. The upper bits are programmed in the STATUS/ID register. The lowest
bit is cleared if the source of the interrupt is a software Interrupt, and set for all other interrupt
sources. Consult the Universe Users Manual for a more in depth explanation.
VMEbus Reset Options
When the front panel Reset switch is toggled, the XVME 689-VR7 can perform the
following reset options:
1.
Reset the VME backplane only.
2.
Reset the XVME 689-VR7 CPU only.
3.
Reset both.
4.
Reset neither.
See Switch Settings in section 3 of this manual for information on how to configure
SW1 for the Reset options.
Software-Selectable Byte-Swapping Hardware
The VMEbus can be used to communicate to either Intel based modules or a Motorola based
modules, these two companies have created data transaction that use different byte ordering in their
data storage. A hardware approach to swapping these byte orders is a faster solution when compared
to a software only byte swapping method. Software selectable byte-swapping hardware is integrated
into the XVME 689-VR7 to allow for the difference between the Intel and Motorola byte-ordering
schemes, allowing easy communication over the VMEbus. The byte-swapping package incorporates
several buffers either to pass data straight through or to swap the data bytes as they are passed
through.
Note
The configurable byte-swapping hardware does not support 64-bit byte-
swapping. If needed, this should be implemented through software.
Byte-Ordering Schemes
The Motorola family of processors stores data with the least significant byte located at the highest
address and the most significant byte at the lowest address. This is referred to as a big-endian bus and
is the VMEbus standard. The Intel family of processors stores data in the opposite way, with the least
significant byte located at the lowest address and the most significant byte located at the highest
address. This is referred to as a little-endian (or PCI) bus. This fundamental difference is illustrated in
Figure 4-1, which shows a 32-bit quantity stored by both architectures, starting at address
M
.
Summary of Contents for XVME-689-VR7
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