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Installation and Setup

2-1

Chapter 2 – Installation and Setup

Board Layout

This chapter provides information on configuring the XVME 689-VR7 modules. It also provides information on
installing the XVME 689-VR7 into a backplane and enabling the Ethernet controller.

Fig. 2-1 shows the jumper, switch, and connector locations on the XVME 689-VR7.

Summary of Contents for XVME-689-VR7

Page 1: ...i XVME 689 VR7 Single Slot VMEbus Intel Celeron M Processor Module User Manual 2008 XEMBEDDED INC Printed in the United States of America...

Page 2: ...and which will provide protection for the apparatus with regard to electromagnetic immunity This enclosure must be fully shielded An example of such an enclosure is a Schroff 7U EMC RFI VME System ch...

Page 3: ...Statement This product has been manufactured to satisfy environmental protection requirements where possible Many of the components used structural parts printed circuit boards connectors batteries e...

Page 4: ......

Page 5: ...Panel Layout 2 5 Connectors 2 6 COM1 and COM4 J4 Pin Definitions 2 10 VMEbus P2 Connector 2 12 VMEbus P2 Connector 2 13 Installing the XVME 689 VR7 into a Backplane 2 18 Enabling the PCI Ethernet Con...

Page 6: ...ftware Selectable Byte Swapping Hardware 4 7 Chapter 5 XVME 990 VR7 Rear Transition Module 5 1 Connectors 5 2 Serial ATA hard drive Interface 5 3 Appendix A SDRAM and Battery Installation 1 Memory Typ...

Page 7: ...ion 4 8 Figure 4 3 Maintaining Numeric Consistency 4 9 Figure 4 4 Maintaining Address Consistency 4 10 Table 1 1 Maximum Video Modes Supported 1 3 Table 1 2 XVME 689 VR7 CPU configurations 1 9 Table 1...

Page 8: ...10 100 1000 Base T Ethernet controllers with front panel RJ 45 connectors with isolated ground or selectable out the P0 to support rear Ethernet or Vita 31 1 Type I II Compact Flash site on optional c...

Page 9: ...e carrier modules can be stacked to allow for up to five 5 PMC sites on one XVME 689 VR7 PCI X or PCI extended is an enhanced version of PCI Peripheral Component Interconnect computer bus Although PCI...

Page 10: ...is switched to the rear optional P0 no lights are available to indicate link or speed The use of the XVME 990 VR7 is required to connect RJ 45 cables to the rear of the XVME 689 VR7 processor boards...

Page 11: ...terminal in a single row Because the connector includes the shielding ground pins very little crosstalk is introduced Note that the receiving terminal uses extended connectors for the 3 ground signal...

Page 12: ...dule IF a mouse is not required a keyboard can be connected directly to the PS 2 port The keyboard and mouse are controlled in the SMC SCH3114 LPC Super I O PMC Expansion The XVME 689 VR7 provides an...

Page 13: ...o solve this problem Xembedded has developed extensive Board Support Packages BSPs that simplify the integration of VMEbus data into PC software applications Xembedded s BSPs provide users with an eff...

Page 14: ...al 40 to 85 C Humidity 10 to 90 RH non condensing 10 to 90 RH non condensing Shock 30 g peak acceleration 11 msec duration 50 g peak acceleration 11 msec duration Vibration 5 2000 Hz 0 015 0 38mm peak...

Page 15: ...r module Compact Flash One on board Compact flash site via optional carrier module Floppy Drive Via P2 to XVME 977 PMC Site On board 66 MHz 64 Bit PMC PCI X with front and P0 I O Access Site is 3 3V i...

Page 16: ...configurations Memory configurations Y 1 VME 64 IEEE 1101 1 Std legacy handles w o VMEbus P0 X 1 for 256 MB ECC DRR SDRAM Y 2 VME 64 IEEE 1101 10 Compact PCI type handles w o VMEbus P0 X 2 for 512 MB...

Page 17: ...nly RS 232 two ports of SATA 150 LPT1 1 USB port Audio in out and Analog Video out XVME 976 209 PMC Carrier module with two PMC module sites The XVME 976 209 allows for stacking of a second XVME 976 2...

Page 18: ...yout This chapter provides information on configuring the XVME 689 VR7 modules It also provides information on installing the XVME 689 VR7 into a backplane and enabling the Ethernet controller Fig 2 1...

Page 19: ...sources auto SYSCON JP4 A B XVME 689 VR7 can reset VMEbus XVME 689 VR7 cannot reset VMEbus JP5 A B Normal Clear CMOS JP6 A B Boot from FLASH Boot from ROM JP7 A B Orb ground not connected to logic gro...

Page 20: ...tch SW1 Functions Position Open Closed 1 Do not respond to SYSRESET Respond to SYSRESET 2 Toggle switch does not cause SYSRESET Toggle switch causes SYSRESET 3 SYSFAIL asserted on Power Up SYSFAIL not...

Page 21: ...r Register This register controls watchdog timer operation Table 2 5 Watchdog Timer Register Settings Bit Signal Result 0 RESERVED Reserved 1 RESERVED Reserved 2 RESERVED Reserved 3 RESERVED Reserved...

Page 22: ...anel Layout Panel LEDs and Switch The reset switch can be enabled to reset see the setup of Sw 1 shown in Figure 2 2 and table 2 2 This switch can be configured to either just reset the XVME 689 VR7 o...

Page 23: ...e XVME 689 VR7 connectors Refer to the EMC warning at the beginning of this manual before attaching cables Keyboard Mouse Port Connector P7 Figure 2 7 Table 2 7 Keyboard Port Connector Pin out Pin Sig...

Page 24: ...optional available at order time only PO connector for either Vita 31 1 switch fabric over the Vita 31 1 compliant backplane or Ethernet out the XVME 990 VR7 2 rear transition module The Vita 31 1 and...

Page 25: ...ar of the VMEbus in the same slot as the XVME 689 VR7 and allows for standard connections to off board devices The XVME 990 VR7 provides a standard SVGA connector for rear access Figure 2 9 SVGA Conne...

Page 26: ...orts USB 2 and 3 are routed out the VMEbus P2 connector and can be accesses either directly off the VMEbus P2 connector using the pin assignment shown in Fig 2 10 The USB 5 V supplies are protected wi...

Page 27: ...e out the VMEbus P2 connector and when the XVME 990 VR7 rear transition module is in place com port 2 and 3 uses a DB 9 connector See below for connector layout and pin descriptions Figure 2 11 RJ 45...

Page 28: ...22 DMARQ 32 PDIAG 3 RESET 13 DD3 23 GROUND 33 DA0 4 GROUND 14 DD12 24 DIOW 34 DA2 5 DD7 15 DD2 25 DIOR 35 CS0 6 DD8 16 DD13 26 GROUND 36 CS1 7 DD6 17 DD1 27 IORDY 37 DASP 8 DD9 18 DD14 28 GROUND 38 3...

Page 29: ...GND WRITE BR2 AM5 15 SDB15 GND BR3 A23 GA3 16 GND DTACK AM0 A22 17 SDBP1 GND AM1 A21 GA4 18 GND AS AM2 A20 19 RSVBUS5 GND AM3 A19 RSVBU1 20 GND IACK GND A18 21 RSVBUS6 IACKIN NC A17 RSVBU2 22 GND IAC...

Page 30: ...IN SATA_RXN0 VD17 SATA_RXN1 LPT1_D5 16 GND GND VD18 GND LPT1_D6 17 LPT1_ACK AUD_LINE_OUT_L VD19 RST_BUT LPT1_D7 18 GND KYBD DATA VD20 KYBD CLK LPT1_BUSY 19 LPT1_SLCT MOUSE DATA VD21 MOUSE CLK LPT1_PE...

Page 31: ...Y N C N C PMC I O 21 PMC I O 7 9 GND IDE_PIORDR IDE_PDCS3 N C PMC I O 22 PMC I O 8 10 GND IDE_PIORDW IDE_PDA2 N C PMC I O 23 PMC I O 35 11 GND IDE_PDD0 IOCS16 N C PMC I O 24 PMC I O 9 12 GND IDE_PDD1...

Page 32: ...LK P D 41 AD 23 2 TRST P D 42 AD 22 3 TMS P U 43 AD 21 4 TDO NC 44 AD 20 5 TDI P U 45 AD 19 6 12v 46 AD 18 7 12V 47 AD 17 8 NC 48 AD 16 9 NC 49 BE2 10 12V 50 FRAME 11 12V 51 IRDY 12 NC 52 TRDY 13 NC 5...

Page 33: ...8 5V 7 BUSMODE1 39 GND 8 5V 40 PLOCK 9 INTD 41 SDONE 10 PCI RSVD14B 42 SBO 11 GND 43 PAR 12 PCI RSVD14A 44 GND 13 PCICLK 45 V_I O 14 GND 46 AD 15 15 GND 47 AD 12 16 GNT 48 AD 11 17 REQ 49 AD 9 18 5V 5...

Page 34: ...48 AD 10 17 PCI RSVD19A 49 AD 8 18 GND 50 3 3V 19 AD 30 51 AD 7 20 AD 29 52 PMC RSVD_PN2 52 21 GND 53 3 3V 22 PAD 26 54 PMC RSVD_PN2 54 23 PAD 24 55 NC 24 3 3V 56 GND 25 IDSEL 57 NC 26 AD 23 58 NC 27...

Page 35: ...bus and all related external power supplies 1 Disconnect all power supplies to the backplane and the card cage Disconnect the power cable 2 Make sure backplane 5 rows 160 pin connectors P1 and P2 are...

Page 36: ...y cable VGA USB cable USB Ethernet cable 10 100 1000T Serial devices COM 1 COM 3 Parallel device LPT1 PMC card PMC Note The floppy drive and hard drive are either cabled across P2 to an XVME 977 or an...

Page 37: ...d the applicable Ethernet driver for your operating system from the Documentation and Support Library CD included with the XVME 689 VR7 For best results always use the supplied drivers Ethernet RJ 45...

Page 38: ...y Move the cursor down several lines a full window s worth scrolling the window as necessary HOME key Move the cursor to the first configurable field in the current menu scrolling the window as necess...

Page 39: ...ipheral devices attached If drives are connected their values will be shown 3 1 Main Setup Menu This Main menu System Summary provides information about the BIOS processor system memory and allows the...

Page 40: ...onds or type zeros in front of numbers Real Time Clock MM DD YYYY Sets the real time clock for the month MM day DD and year YYYY The valid values in this field are 01 01 1981 through 12 31 2099 Use TA...

Page 41: ...s Enter System Reload Factory Defaults and Restart Enter Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 2 Save Restore and Restart Menu To select any of these options position...

Page 42: ...Fastest support mode Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 3 System Boot Configuration Menu When the BIOS completes POST it follows this list attempting to process ea...

Page 43: ...rlier in this section and then goes down the list and tries to perform the actions in order During this boot phase if the list item is a drive an attempt is made to boot from the boot record of that d...

Page 44: ...talled IDE 0 Mode Multi word DMA mode PIO Mode MULTI Word DMA Mode UDMA_Mode 40 Conductor Cable UDMA_Mode 80 Conductor Cable Fastest Supported Mode IDE 1 Type Autoconfig AutoConfig AutoConfig Physical...

Page 45: ...nfiguration section describes the type of hard drive equipment that is connected to the motherboard including the cable type IDE drives or actually more properly Parallel ATA PATA drives are connected...

Page 46: ...est Disabled Click During Memory Test Enabled Clear Memory During Test Disabled Post Error Control Pause on POST Errors Enabled POST User Interface POST Display Messages Enabled POST Operator Prompt E...

Page 47: ...ly on cleared memory to operate properly The following table describes the settings associated with the POST setup menu s Error Control section Pause on POST Errors Enable pause when errors are detect...

Page 48: ...tered and this option is disabled When left unattended this is a straightforward way of having POST exercise system memory and peripherals without requiring a boot to a drive with an operating system...

Page 49: ...ed to configure Plug n Play a legacy BIOS initiative used to support operating systems such as Windows95 Windows98 and WindowsNT ACPI has largely replaced this feature however it is necessary for plat...

Page 50: ...isabled IRQ 2 Disabled IRQ 3 Enabled IRQ 4 Enabled IRQ 5 Enabled IRQ 6 Disabled IRQ 7 Enabled IRQ 8 Disabled IRQ 9 Enabled IRQ 10 Enabled IRQ 11 Enabled IRQ 12 Disabled IRQ 13 Enabled IRQ 14 Disabled...

Page 51: ...nfigure the devices and instead defer assignment of resources such as DMA I O memory and IRQs to the PnP OS When disabled the BIOS performs conflict detection and resolution and assigns resources for...

Page 52: ...hannel 4 Mode Printer Serial Port 1 Enabled Address 3f8h IRQ IRQ 4 Serial Port 2 Enabled Address 2f8h IRQ IRQ 3 Serial Port 3 Enabled Address 3e8h IRQ IRQ 3 Embedded BIOS 2000 V6 0 5 Copyright 2006 Ge...

Page 53: ...S programs that do not use BIOS to access the COM ports Keyboard Enable PC AT or PS 2 keyboard controller Mouse Enable PC AT or PS 2 mouse portion of keyboard controller GPIO device name Enable GPIO d...

Page 54: ...tic P7 Geyserville Enabled Microcode Update Enabled Embedded BIOS 2000 V6 0 5 Copyright 2006 General Software Inc Figure 3 7 BIOS Feature Configuration The following table describes each setting in th...

Page 55: ...ncluding the chassis motherboard layout type of CPU and DRAM sticks to applications such as WfM which runs on PXE in the preboot environment Manufacturing Mode Enable automatic entry into manufacturin...

Page 56: ...base Disk I O Disabled Firmbase User Registry Disabled Firmbase User Section Disabled Firmbase Network Stack Disabled Firmbase User Shell Disabled Firmbase Application Suite Disabled Embedded BIOS 200...

Page 57: ...OEM which may include SNMP SMTP TELNETD and HTTP server Firmbase Desktop Enables Firmbase Technology graphical shell Firmbase User Shell Enables Firmbase Technology command line interpreter a multi us...

Page 58: ...ed to achieve acceptable performance However to diagnose certain problems related to caching in the system such as multiprocessing systems it may be desirable to disable this setting Keyboard Numlock...

Page 59: ...t the stimulation of the system includes reading a range of sectors into a memory buffer and writing the same data back to the same range of sectors for safety Thus this feature is theoretically nonde...

Page 60: ...e same data back to the same range of sectors for safety Thus this feature is theoretically nondestructive WARNING BECAUSE THE OEM S ADAPTATION AND OTHER FACTORS ARE BEYOND GENERAL S CONTROL YOU ARE A...

Page 61: ...must be provided by the module installed in the system controller slot left most slot The status of the XVME 689 VR7 system resources is reported in a read only field Note The BERR timeout is the VMEb...

Page 62: ...eout Choices are 16 s 32 s 64 s default 128 s 256 s 512 s 1024 s and Disabled Arbitration Mode This field is used to set the VMEbus arbitration mode Choices are Priority Single default or Round Robin...

Page 63: ...re reserved for BIOS use See p Error Bookmark not defined for more details System Configuration Utility Features Misc VME_Master VME_Slave FrontPanelConfig VMEbus Slave Configuration Slave 1 Disable S...

Page 64: ...ilable for VMEbus Standard Address Space Base Address High Nibble Base Address Med Nibble Base Address Low Nibble These fields determine the base VMEbus address prefix for the first 12 bits of the add...

Page 65: ...s System Configuration Utility Features Misc VME_Master VME_Slave FrontPanelConfig Front Panel Config Video routed to front VGA Port or rear Overridded by JP8 on Video Routed to Front or Rear Front Bo...

Page 66: ...00BFFFF 128K VGA DRAM MEMORY 00000000 0009FFFF 640K DRAM See Intel 6300ESB data sheet for a description for optional settings for setting memory holes or gaps within Memory map area The PCI devices ar...

Page 67: ...3F6 Primary IDE Controller Generates CS3 3F8 3FF Serial port 1 note 1 400 47F Industry Pack IP I O 480 4BF Industry Pack IP ID 4D0h ELCR1 Edge or level triggered 4D1h ELCR2 Edge or level triggered CF...

Page 68: ...RQ9 PCI X Video IRQ10 Onboard PMC X IRQ11 PCI Expansion to PMC 1 IRQ11 Ethernet 2 IRQ12 Mouse IRQ13 Math Coprocessor reserved IRQ14 Primary IDE IRQ15 Secondary IDE The above interrupt mapping is one p...

Page 69: ...t to AGP Bridge Virtual PCI to PCI Device 1 Intel 855GME GMCH Only Integrated Graphics Controller IGD Device 2 0000 0000 6300ESB 244e 25A1 25A2 25A9 25AD 25A4 25A6 25A7 25AB 25AC 25AE 25A3 or 25B0 808...

Page 70: ...p 2 2 VMEbus Master Interface The XVME 689 VR7 can be either a VMEbus master by accessing a PCI slave channel or the DMA channel initiates a transaction There are 8 PCI slave images The first PCI sla...

Page 71: ...ge be enabled If a slave image is going to be remapped disable the slave image first then reset the address After the image is configured correctly enable the image again The VMEbus slave cycle become...

Page 72: ...se different byte ordering in their data storage A hardware approach to swapping these byte orders is a faster solution when compared to a software only byte swapping method Software selectable byte s...

Page 73: ...cture and byte swapping hardware to reverse the Universe chip byte lane swapping Contact Tundra at www tundra com for a PDF version of the Universe manual Figure 4 2 shows address invariant translatio...

Page 74: ...rable for transferring integer data floating point data pointers etc Consider the long word value 12345678h stored at address M by both the XVME 689 VR7 and the VMEbus as shown in Figure 4 3 Figure 4...

Page 75: ...te oriented data such as strings or video image data Consider the example of transferring the string Text to the VMEbus memory using a 32 bit transfer in Figure 4 4 Figure 4 4 Maintaining Address Cons...

Page 76: ...e RTMs are used with the XVME 689 VR7 some functions normally available at the rear or will not be available The XVME 990 VR7 Drive Adapter Module is used to connect an external DVD CD ROM or hard dri...

Page 77: ...35 DA0 16 HD14 36 DA2 17 HD0 37 CS1P 18 HD15 38 CS3P 19 GND 39 IDEATP 20 KEY NC 40 GND Caution The IDE controller supports enhanced PIO modes which reduce the cycle times for 16 bit data transfers to...

Page 78: ...face Fig 5 2 SATA connector Mating connector to connector on the XVME 990 VR7 is Molex 67489 9005 VMEbus P2 Pin Row z Signal Name on P2 SATA connector on the XVME 990 VR7 SATA Signal Name Z1 SATA_TXP0...

Page 79: ...SELECT 8 GND GND A28 HD6 PAUTOFEED 9 SATA_TXP1 DTR2 A29 HD7 PPERROR 10 GND TXD2 A30 HD8 PINIT 11 SATA_TXN1 RXD2 A31 HD9 PSELIN 12 GND DCD2 GND HD10 PPD 0 13 SATA_RXN1 AUD_LINE_IN_L 5V HD11 PPD 1 14 GN...

Page 80: ...of the interconnect of VMEbus P2 to P3 Pin Number Row a Row b Row c 1 5V IDERST1 2 GND HD0 3 VME_RETRY HD1 4 RI2 A24 HD2 5 CTS2 A25 HD3 6 RTS2 A26 HD4 7 DSR2 A27 HD5 8 GND A28 HD6 9 DTR2 A29 HD7 10 TX...

Page 81: ...is not supplied by the XVME 990 VR7 Table 5 5 XVME 990 VR7 FDD1 Connector Pin out Pin Signal Pin Signal 1 GND 18 FDIRC 2 FRWC 19 GND 3 GND 20 FSTEP 4 NC 21 GND 5 KEY NC 22 FWD 6 NC 23 GND 7 GND 24 FWE...

Page 82: ...additional ground planes that can handle the faster interface speeds Intermitted hard drive functions can be traced back to the use of a standard 40 conductor 40 pin cable The IDE controller supports...

Page 83: ...rd connector as shown in Figure 2 10 below The other two USB ports USB 2 and 3 are routed out the VMEbus P2 connector and can be accesses either directly off the VMEbus P2 connector using the pin assi...

Page 84: ...O4 PMC_IO3 PMC_IO2 PMC_IO1 IDEATP 8 PMC_IO10 PMC_IO9 PMC_IO8 PMC_IO7 PMC_IO6 GND 9 PMC_IO15 PMC_IO14 PMC_IO13 PMC_IO12 PMC_IO11 GND 10 PMC_IO20 PMC_IO19 PMC_IO18 PMC_IO17 PMC_IO16 GND 11 PMC_IO25 PMC_...

Page 85: ...O 17 43 PMC I O 18 10 PMC I O 19 44 PMC I O 20 11 PMC I O 21 45 PMC I O 22 12 PMC I O 23 46 PMC I O 24 13 PMC I O 25 47 PMC I O 26 14 PMC I O 27 48 PMC I O 28 15 PMC I O 29 49 PMC I O 30 16 PMC I O 31...

Page 86: ...990 VR7 If the VMEbus has Vita 31 1 Capability the rear Ethernet ports can not be used they will conflict with the VMEbus switch fabric connections on the back plane Fig 5 4 RJ 45 Connector Table 5 11...

Page 87: ...e on either the front panel or out the VMEbus P2 The table below shows the pin out of the standard video connector and also the VMEbus P2 pin out for the rear access of video The XVME 990 VR7 rear tra...

Page 88: ...to a standard printer Table 5 14 Parallel Port Connector Pin out showing connections to VMEbus P2 and 26 pin header on the XVME 990 VR7 P2 VMEbus Connector 26 Pin header Signal P2 VMEbus Connector 26...

Page 89: ...cts on the rear transition module are line level inputs and outputs To drive a speaker an amplifier will be needed Table 5 15 Showing VMEbus P2 to Audio plugs VMEbus P2 Pin Number Row a 13 AUD_LINE_IN...

Page 90: ...L485L2925C B3 200196 SODIMM 2GB DDR333 Virtium Installing SDRAM Follow these steps to install the SODIMM 1 Follow standard antistatic procedures using a wrist strap to minimize the chance of damaging...

Page 91: ...connectors etc 10 Power up the unit and make sure that the memory is recognized during boot up on the Boot time diagnostic screen that can be turned on in the BIOS see p Error Bookmark not defined Mod...

Page 92: ...te swapping 2 5 4 7 4 9 4 10 Compact Flash drive 1 4 compliance VMEbus 1 9 connectors CPU fan power 2 17 keyboard port 2 6 PMC 2 16 RJ 45 10 100 Base T 2 20 5 11 Univeral Serial Bus USB 2 9 5 8 VGA 2...

Page 93: ...ainboard 3 24 4 5 keyboard interface 1 5 keyboard port connector 2 6 LED BIOS register 2 4 memory map 4 1 memory SDRAM 1 9 P1 connector XVME 973 1 5 2 P3 connector XVME 973 1 5 6 P4 connector XVME 973...

Page 94: ...dware 1 9 switch settings 2 3 system resources 3 24 4 5 Universal Serial Bus USB port 2 9 5 8 Universe chip 4 5 4 7 4 8 4 9 4 10 VGA connector 2 8 5 12 VME interface 4 5 VMEbus compliance 1 9 interfac...

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