FOR MOBILE APPLICATIONS
W25Q256FV
Publication Release Date: May 13, 2012
- 46 - Preliminary - Revision M1
8.2.18
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO
0
and IO
1
. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23/A31-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23/A31-0), as shown in Figure 22a.
The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 22b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh/FFFFFh on IO0 for the next instruction (16/20 clocks), to ensure M4 = 1
and return the device to normal operation.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (BBh)
8
9
10
12
13
14
24
25
26
27
28
29
30
31
6
4
2
0
*
*
23
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
0
32
33
34
35
36
37
38
39
7
5
3
1
*
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
*
*
IOs switch from
Input to Output
6
7
22
20
18
16
23
21
19
17
14
12
10
8
15
13
11
9
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
11
15
16
17
18
20
21
22
19
23
1
A23-16
A15-8
A7-0
M7-0
Byte 1
Byte 2
Byte 3
Byte 4
= MSB
*
*
Figure 22a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4
≠
10, SPI Mode only)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
