FOR MOBILE APPLICATIONS
W25Q256FV
Publication Release Date: May 13, 2012
- 44 - Preliminary - Revision M1
8.2.16
Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO
0
, IO
1
, IO
2
, and IO
3
. The Quad Enable (QE) bit in Status
Register-2 must be set to 1 before the device will accept the Fast Read Quad Output Instruction. The Fast
Read Quad Output Instruction allows data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of F
R
(see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24/32-bit
address as shown in Figure 20. The dummy clocks allow the device's internal circuits additional time for
setting up the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock.
/CS
CLK
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Instruction (6Bh)
High Impedance
8
9
10
28
29
30
32
33
34
35
36
37
38
39
4
0
24-Bit Address
23
22
21
3
2
1
0
*
31
31
/CS
CLK
Dummy Clocks
0
40
41
42
43
44
45
46
47
5
1
High Impedance
4
5
High Impedance
High Impedance
6
2
7
3
High Impedance
High Impedance
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
Byte 1
6
7
1
6
2
7
3
Byte 2
Byte 3
Byte 4
IO
0
switches from
Input to Output
IO
0
IO
1
IO
2
IO
3
IO
0
IO
1
IO
2
IO
3
= MSB
*
Figure 20. Fast Read Quad Output Instruction (SPI Mode only)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
