FOR MOBILE APPLICATIONS
W25Q256FV
- 51 -
M7-0
/CS
CLK
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
3
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
4
0
5
1
6
2
7
3
A15-8
A7-0
Byte 1
Byte 2
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
10
11
12
13
14
4
5
6
7
15
IOs switch from
Input to Output
Byte 3
Dummy
Dummy
Figure 24b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. Refer to section 8.2.24 for detail descriptions.
