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FOR MOBILE APPLICATIONS

W25Q256FV

Publication Release Date: May 13, 2012

- 82 - Preliminary - Revision M1

8.2.44

Set Read Parameters (C0h)

In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to
configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read
with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read
with Wrap (0Ch)” instruction.

In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks
for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the
Instruction Table 1-3 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with Wrap (77h)”
instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to
QPI mode.

The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast
Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the
device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to
any 0Bh, EBh or 0Ch instructions.

P5 – P4

DUMMY

CLOCKS

MAXIMUM

READ FREQ.

MAXIMUM

READ FREQ.

(A[1:0]=0,0)

MAXIMUM

READ FREQ.

(A[1:0]=0,0

VCC=3.0V~3.6V)

P1 – P0

WRAP

LENGTH

0 0

2 33MHz 50MHz 60MHz

0 0

8-byte

0 1

4 66MHz 80MHz 104MHz

0 1

16-byte

1 0

6 104MHz 104MHz 133MHz

1 0

32-byte

1 1

8 104MHz 104MHz 133MHz

1 1

64-byte

/CS

CLK

Mode 0

Mode 3

0

1

2

3

IO

0

IO

1

IO

2

IO

3

C0h

Read

Parameters

P4

P0

P5

P1

P6

P2

P7

P3

Instruction

Mode 0

Mode 3

Figure 48. Set Read Parameters Instruction (QPI Mode only)

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Summary of Contents for SpiFlash W25Q256FV

Page 1: ...FOR MOBILE APPLICATIONS W25Q256FV Publication Release Date May 13 2012 Preliminary Revision M1 3V 256M BIT SERIAL FLASH MEMORY WITH DUAL QUAD SPI QPI For Mobile Applications...

Page 2: ...Reset Hardware RESET pin 11 6 2 Write Protection 12 7 STATUS AND CONFIGURATION REGISTERS 13 7 1 Status Registers 13 7 1 1 Erase Write In Progress BUSY Status Only 13 7 1 2 Write Enable Latch WEL Statu...

Page 3: ...ble 5 QPI Instructions 3 Byte Address Mode 27 8 1 7 Instruction Set Table 6 QPI Instructions 4 Byte Address Mode 27 8 2 Instruction Descriptions 29 8 2 1 Write Enable 06h 29 8 2 2 Write Enable for Vol...

Page 4: ...Security Registers 42h 80 8 2 43 Read Security Registers 48h 81 8 2 44 Set Read Parameters C0h 82 8 2 45 Burst Read with Wrap 0Ch 83 8 2 46 Enter QPI Mode 38h 84 8 2 47 Exit QPI Mode FFh 85 8 2 48 Ind...

Page 5: ...10 PACKAGE SPECIFICATIONS 98 Publication Release Date May 13 2012 4 Preliminary Revision M1 10 1 8 Pad WSON 8x6 mm Package Code E 98 11 ORDERING INFORMATION 99 11 1 Valid Part Numbers and Top Side Ma...

Page 6: ...mory access with as few as 8 clocks of instruction overhead to read a 24 bit address allowing true XIP execute in place operation A Hold pin Write Protect pin and programmable write protection with to...

Page 7: ...Figure 1a W25Q256FV Pad Assignments 8 pad WSON 8x6 mm Package Code E 3 2 Pad Description WSON 8x6 mm PAD NO PAD NAME I O FUNCTION 1 CS I Chip Select Input 2 DO IO1 I O Data Output Data Input Output 1...

Page 8: ...tions require the non volatile Quad Enable bit QE in Status Register 2 to be set When QE 1 the WP pin becomes IO2 and HOLD pin becomes IO3 4 3 Write Protect WP The Write Protect WP pin can be used to...

Page 9: ...0FFFh Sector 0 4KB xx0000h xx00FFh xx1F00h xx1FFFh Sector 1 4KB xx1000h xx10FFh xx2F00h xx2FFFh Sector 2 4KB xx2000h xx20FFh xxDF00h xxDFFFh Sector 13 4KB xxD000h xxD0FFh xxEF00h xxEFFFh Sector 14 4KB...

Page 10: ...ut pin to serially write instructions addresses or data to the device on the rising edge of CLK The DO output pin is used to read data or status from the device on the falling edge of CLK SPI bus oper...

Page 11: ...rmance in an XIP environment Standard Dual Quad SPI mode and QPI mode are exclusive Only one mode can be active at any given time Enter QPI 38h and Exit QPI FFh instructions are used to switch between...

Page 12: ...and Serial Clock CLK are ignored The Chip Select CS signal should be kept active low for the full duration of the HOLD operation to avoid resetting the internal logic state of the device 6 1 7 Softwar...

Page 13: ...Write Enable Latch WEL set to a 0 A Write Enable instruction must be issued before a Page Program Sector Erase Block Erase Chip Erase or Write Status Register instruction will be accepted After compl...

Page 14: ...Block Protect Bits Volatile Non Volatile Writable Write Enable Latch Status Only Erase Write In Progress Status Only Figure 4a Status Register 1 7 1 1 Erase Write In Progress BUSY Status Only BUSY is...

Page 15: ...on Once CMP is set to 1 previous array protection set by TB BP3 BP2 BP1 and BP0 will be reversed For instance when CMP 0 a top 64KB block can be protected while the rest of the array is not when CMP 1...

Page 16: ...of LB3 1 is 0 Security Registers are unlocked LB3 1 can be set to 1 individually using the Write Status Register instruction LB3 1 are One Time Programmable OTP once it s set to 1 the corresponding 25...

Page 17: ...n Volatile Writable The ADP bit is a non volatile bit that determines the initial address mode when the device is powered on or reset This bit is only used during the power on or device reset initiali...

Page 18: ...function should be implemented on the hardware pin When HOLD RST 0 factory default the pin acts as HOLD when HOLD RST 1 the pin acts as RESET However HOLD or RESET functions are only available when Q...

Page 19: ...1 448 thru 511 01C00000h 01FFFFFFh 4MB Upper 1 8 0 1 0 0 0 384 thru 511 01800000h 01FFFFFFh 8MB Upper 1 4 0 1 0 0 1 256 thru 511 01000000h 01FFFFFFh 16MB Upper 1 2 1 0 0 0 1 0 00000000h 0000FFFFh 64K...

Page 20: ...00000h 01BFFFFFh 28MB Lower 7 8 0 1 0 0 0 0 thru 383 00000000h 017FFFFFh 24MB Lower 3 4 0 1 0 0 1 0 thru 255 00000000h 00FFFFFFh 16MB Lower 1 2 1 0 0 0 1 1 thru 511 00010000h 01FFFFFFh 32 704KB Upper...

Page 21: ...Revision M1 1 18 W25Q256FV Individual Block Memory Protection WPS 1 7 Figure 4d Individual Block Sector Locks Notes 1 Individual Block Sector protection is only valid when WPS 1 2 All individual block...

Page 22: ...esses will be executed within that region When A24 1 the upper 128Mb memory array 01000000h 01FFFFFFh will be selected If the device powers up with ADP bit set to 1 or an Enter 4 Byte Address Mode B7h...

Page 23: ...ocol 3 Byte Address Mode ADS 0 4 Byte Address Mode ADS 1 Standard Dual Quad SPI Instruction Set Table 1 2 Instruction Set Table 1 3 QPI Instruction Set Table 4 5 Instruction Set Table 4 6 Instructions...

Page 24: ...00h MF7 MF0 ID7 ID0 JEDEC ID 9Fh MF7 MF0 ID15 ID8 ID7 ID0 Global Block Lock 7Eh Global Block Unlock 98h Enter QPI Mode 38h Enter 4 Byte Address Mode B7h Exit 4 Byte Address Mode E9h Enable Reset 66h R...

Page 25: ...Register 5 44h A23 A16 A15 A8 A7 A0 Program Security Register 5 42h A23 A16 A15 A8 A7 A0 D7 D0 D7 D0 3 Read Security Register 5 48h A23 A16 A15 A8 A7 A0 Dummy D7 D0 Individual Block Lock 36h A23 A16...

Page 26: ...ram Security Register 5 42h A31 A24 A23 A16 A15 A8 A7 A0 D7 D0 D7 D0 3 Read Security Register 5 48h A31 A24 A23 A16 A15 A8 A7 A0 Dummy D7 D0 Individual Block Lock 36h A31 A24 A23 A16 A15 A8 A7 A0 Indi...

Page 27: ...r 2 35h S15 S8 2 Write Status Register 2 31h S15 S8 Read Status Register 3 15h S23 S16 2 Write Status Register 3 11h S23 S16 Read Extended Addr Register C8h EA7 EA0 2 Write Extended Addr Register C5h...

Page 28: ...39h A23 A16 A15 A8 A7 A0 Read Block Lock 3Dh A23 A16 A15 A8 A7 A0 L7 L0 8 1 7 Instruction Set Table 6 QPI Instructions 4 Byte Address Mode 14 Data Input Output Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte...

Page 29: ...I data output format IO0 D6 D4 D2 D0 IO1 D7 D5 D3 D1 8 Quad SPI address input format Set Burst with Wrap input format IO0 A20 A16 A12 A8 A4 A0 M4 M0 IO0 x x x x x x W4 x IO1 A21 A17 A13 A9 A5 A1 M5 M1...

Page 30: ...Register 50h The non volatile Status Register bits described in section 7 1 can also be written to as volatile bits This gives more flexibility to change the system configuration and memory protectio...

Page 31: ...t or QPI Mode right 8 2 4 Read Status Register 1 05h Status Register 2 35h Status Register 3 15h The Read Status Register instructions allow the 8 bit Status Registers to be read The instruction is en...

Page 32: ...ruction must have been executed prior to the Write Status Register instruction Status Register bit WEL remains 0 However SRP1 and LB 3 1 cannot be changed from 1 to 0 because of the OTP protection for...

Page 33: ...the QPI mode because QE 1 is required for the device to enter and operate in the QPI mode Refer to section 7 1 for Status Register descriptions Factory default for all status Register bits are 0 Figur...

Page 34: ...rite Status Register 1 01h instruction will only program the Status Register 1 the Status Register 2 will not be affected Previous generations will clear CMP and QE bits 33 IO0 DO IO1 CS CLK DI Mode 0...

Page 35: ...ed Address Register instruction is entered by driving CS low and shifting the instruction code C8h into the DI pin on the rising edge of CLK The Extended Address Register bits are then shifted out on...

Page 36: ...ction code C5h and then writing the Extended Address Register data byte as illustrated in Figure 11 Upon power up or the execution of a Software Hardware Reset the Extended Address Register bit values...

Page 37: ...s Mode instruction for SPI Mode left or QPI Mode right 8 2 9 Exit 4 Byte Address Mode E9h In order to be backward compatible the Exit 4 Byte Address Mode instruction Figure 13 will only allow 24 bit a...

Page 38: ...ntinuous stream of data This means that the entire memory can be accessed with a single instruction as long as the clock continues The instruction is completed by driving CS high The Read Data instruc...

Page 39: ...te Address instruction will always require 32 bit address to access the entire 256Mb memory The Read Data with 4 Byte Address instruction sequence is shown in Figure 15 If this instruction is issued w...

Page 40: ...circuits additional time for setting up the initial address During the dummy clocks the data value on the DO pin is a don t care CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1 2 3 4 5 6 7 Instruction 0Bh High...

Page 41: ...d Parameter Bits P 5 4 setting the number of dummy clocks can be configured as either 2 4 6 or 8 The default number of dummy clocks upon power up or after a Reset instruction is 2 CS CLK Mode 0 Mode 3...

Page 42: ...matter the device is operating in 3 Byte Address Mode or 4 byte Address Mode the Read Data with 4 Byte Address instruction will always require 32 bit address to access the entire 256Mb memory The Fast...

Page 43: ...accomplished by adding eight dummy clocks after the 24 32 bit address as shown in Figure 18 The dummy clocks allow the device s internal circuits additional time for setting up the initial address Th...

Page 44: ...2 bit address instead of 24 bit address No matter the device is operating in 3 Byte Address Mode or 4 byte Address Mode the Fast Read Dual Output with 4 Byte Address instruction will always require 32...

Page 45: ...dummy clocks after the 24 32 bit address as shown in Figure 20 The dummy clocks allow the device s internal circuits additional time for setting up the initial address The input data during the dummy...

Page 46: ...2 bit address instead of 24 bit address No matter the device is operating in 3 Byte Address Mode or 4 byte Address Mode the Fast Read Quad Output with 4 Byte Address instruction will always require 32...

Page 47: ...e Continuous Read Mode bits M5 4 1 0 then the next Fast Read Dual I O instruction after CS is raised and then lowered does not require the BBh instruction code as shown in Figure 22b This reduces the...

Page 48: ...4 2 0 7 5 3 1 IOs switch from Input to Output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 A23 16 A15 8 A7 0 M7 0 Byte 1 Byte 2 Byte 3 Byte 4 0 1 2 3 4 5 6 7 16 1...

Page 49: ...requires 32 bit address instead of 24 bit address No matter the device is operating in 3 Byte Address Mode or 4 byte Address Mode the Fast Read Dual I O with 4 Byte Address instruction will always req...

Page 50: ...FOR MOBILE APPLICATIONS W25Q256FV 49 Figure 23b Fast Read Dual I O with 4 Byte Address Instruction Previous instruction set M5 4 10 SPI Mode only...

Page 51: ...the M3 0 are don t care x However the IO pins should be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O...

Page 52: ...er enable or disable the Wrap Around feature for the following EBh commands When Wrap Around is enabled the data being accessed can be limited to either an 8 16 32 or 64 byte section of a 256 byte pag...

Page 53: ...the data output will follow the Continuous Read Mode bits immediately Continuous Read Mode feature is also available in QPI mode for Fast Read Quad I O instruction Please refer to the description on...

Page 54: ...of 24 bit address No matter the device is operating in 3 Byte Address Mode or 4 byte Address Mode the Fast Read Quad I O with 4 Byte Address instruction will always require 32 bit address to access t...

Page 55: ...mited to either an 8 16 32 or 64 byte section of a 256 byte page The output data starts at the initial address specified in the instruction once it reaches the ending boundary of the 8 16 32 64 byte s...

Page 56: ...be high impedance prior to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O instruction after CS is raised and then lowered does...

Page 57: ...rst with Wrap 77h command can either enable or disable the Wrap Around feature for the following E7h commands When Wrap Around is enabled the data being accessed can be limited to either an 8 16 32 or...

Page 58: ...or to the falling edge of the first data out clock If the Continuous Read Mode bits M5 4 1 0 then the next Fast Read Quad I O instruction after CS is raised and then lowered does not require the E3h i...

Page 59: ...9 13 9 14 10 15 11 A23 16 6 7 4 0 5 1 6 2 7 3 A15 8 A7 0 4 0 5 1 6 2 7 3 Byte 1 Byte 2 4 0 5 1 4 0 5 1 6 2 7 3 6 2 7 3 4 5 6 7 IOs switch from Input to Output Byte 3 8 9 10 11 12 13 4 0 5 1 6 2 7 3 By...

Page 60: ...set by a Set Burst with Wrap instruction all the following Fast Read Quad I O and Word Read Quad I O instructions will use the W6 4 setting to access the 8 16 32 64 byte section within any page To ex...

Page 61: ...vice the addressing will wrap to the beginning of the page and overwrite previously sent data As with the write and erase instructions the CS pin must be driven high after the eighth bit of the last b...

Page 62: ...4 10 15 11 A23 16 6 7 8 9 4 0 5 1 6 2 7 3 A15 8 A7 0 Byte1 Byte 2 Byte 3 4 0 5 1 4 0 5 1 4 0 5 1 6 2 7 3 6 2 7 3 6 2 7 3 10 11 12 13 Byte 255 Byte 256 4 0 5 1 4 0 5 1 6 2 7 3 6 2 7 3 Mode 0 Mode 3 516...

Page 63: ...truction Status Register 1 WEL 1 The instruction is initiated by driving the CS pin low then shifting the instruction code 32h followed by a 24 32 bit address A23 A31 A0 and at least one data byte int...

Page 64: ...ster instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to a...

Page 65: ...ogress the Read Status Register instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished an...

Page 66: ...instruction may still be accessed for checking the status of the BUSY bit The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept...

Page 67: ...lf timed Chip Erase instruction will commence for a time duration of tCE See AC Characteristics While the Chip Erase cycle is in progress the Read Status Register instruction may still be accessed to...

Page 68: ...Page Program operation is on going If the SUS bit equals to 1 or the BUSY bit equals to 0 the Suspend instruction will be ignored by the device A maximum of time of tSUS See AC Characteristics is requ...

Page 69: ...W25Q256FV Publication Release Date May 13 2012 68 Preliminary Revision M1 CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 75h Instruction Mode 0 Mode 3 tSUS Accept instructions Figure 35b Erase Program Suspe...

Page 70: ...SUS bit equals to 0 or the BUSY bit equals to 1 the Resume instruction 7Ah will be ignored by the device The Erase Program Resume instruction sequence is shown in Figure 36a 36b Resume instruction is...

Page 71: ...he power down state will entered within the time duration of tDP See AC Characteristics While in the power down state only the Release Power down Device ID ABh instruction which restores the device to...

Page 72: ...by 3 dummy bytes The Device ID bits are then shifted out on the falling edge of CLK with most significant bit MSB first The Device ID values for the W25Q256FV is listed in Manufacturer and Device Ide...

Page 73: ...n ABh High Impedance 8 9 29 30 31 3 Dummy Bytes 23 22 2 1 0 Mode 0 Mode 3 7 6 5 4 3 2 1 0 32 33 34 35 36 37 38 Device ID Power down current Stand by current MSB Figure 38c Release Power down Device ID...

Page 74: ...wed by a 24 bit address A23 A0 of 000000h After which the Manufacturer ID for Winbond EFh and the Device ID are shifted out on the falling edge of CLK with most significant bit MSB first as shown in F...

Page 75: ...ID values for the W25Q256FV are listed in Manufacturer and Device Identification table If the 24 bit address is initially set to 000001h the Device ID will be read first and then followed by the Manu...

Page 76: ...r and Device Identification table If the 24 bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID The Manufacturer and Device IDs can be rea...

Page 77: ...fting the instruction code 4Bh followed by a four bytes of dummy clocks After which the 64 bit ID is shifted out on the falling edge of CLK as shown in Figure 42 CS CLK DI IO0 DO IO1 Mode 0 Mode 3 0 1...

Page 78: ...then shifted out on the falling edge of CLK with most significant bit MSB first as shown in Figure 43a 43b For memory type and capacity values refer to Manufacturer and Device Identification table CS...

Page 79: ...ion is initiated by driving the CS pin low and shifting the instruction code 5Ah followed by a 24 bit address A23 A0 1 into the DI pin Eight dummy clocks are also required before the SFDP register con...

Page 80: ...f the last byte has been latched If this is not done the instruction will not be executed After CS is driven high the self timed Erase Security Register operation will commence for a time duration of...

Page 81: ...0 1 0 0 0 0 Byte Address Security Register 2 00h 0 0 1 0 0 0 0 0 Byte Address Security Register 3 00h 0 0 1 1 0 0 0 0 Byte Address The Program Security Register instruction sequence is shown in Figur...

Page 82: ...r and continue to increment The instruction is completed by driving CS high The Read Security Register instruction sequence is shown in Figure 47 If a Read Security Register instruction is issued whil...

Page 83: ...t in the Set Burst with Wrap 77h instruction This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode The default Wrap Length after a power up or a Reset instr...

Page 84: ...ary is reached The Wrap Length and the number of dummy clocks can be configured by the Set Read Parameters C0h instruction Dummy CS CLK Mode 0 Mode 3 0 1 IO0 IO1 IO2 IO3 0Ch 2 3 4 5 20 16 12 8 21 17 2...

Page 85: ...inbond serial flash memories See Instruction Set Table 1 3 for all supported SPI commands In order to switch the device to QPI mode the Quad Enable QE bit in Status Register 2 must be set to 1 first a...

Page 86: ...SPI mode an Exit QPI FFh instruction must be issued When the device is switched from QPI mode to SPI mode the existing Write Enable Latch WEL and Program Erase Suspend status and the Wrap Length sett...

Page 87: ...ock bits are volatile bits The default values after device power up or after a Reset are 1 so the entire memory array is being protected To lock a specific block or sector as illustrated in Figure 4d...

Page 88: ...The default values after device power up or after a Reset are 1 so the entire memory array is being protected To unlock a specific block or sector as illustrated in Figure 4d an Individual Block Sect...

Page 89: ...the lock bit value of a specific block or sector as illustrated in Figure 4d a Read Block Sector Lock command must be issued by driving CS low shifting the instruction code 3Dh into the Data Input DI...

Page 90: ...ng edge of CLK and then driving CS high Figure 55 Global Block Lock Instruction for SPI Mode left or QPI Mode right 8 2 52 Global Block Sector Unlock 98h All Block Sector Lock bits can be set to 0 by...

Page 91: ...must be issued in sequence Any other commands other than Reset 99h after the Enable Reset 66h command will disable the Reset Enable state A new sequence of Enable Reset 66h and Reset 99h is needed to...

Page 92: ...s 1 This device has been designed and tested for the specified operation ranges Proper operation outside of these levels is not guaranteed Exposure to absolute maximum ratings may affect device reliab...

Page 93: ...in to CS Low tVSL 1 10 s Time Delay Before Write Instruction tPUW 1 1 10 ms Write Inhibit Threshold Voltage VWI 1 1 0 2 0 V Note 1 These parameters are characterized only VCC tVSL Read Instructions Al...

Page 94: ...VCC 0 9 VCC DO Open 15 mA Current Read Data Dual Quad 80MHz 2 ICC3 C 0 1 VCC 0 9 VCC DO Open 18 mA Current Read Data Dual Output Read Quad Output Read 104MHz 2 ICC3 C 0 1 VCC 0 9 VCC DO Open 20 mA Cur...

Page 95: ...put Rise and Fall Times TR TF 5 ns Input Pulse Voltages VIN 0 1 VCC to 0 9 VCC V Input Timing Reference Voltages IN 0 3 VCC to 0 7 VCC V Output Timing Reference Voltages OUT 0 5 VCC to 0 5 VCC V Note...

Page 96: ...ction tCRLH tCRLL 1 8 ns Clock Rise Time peak to peak tCLCH 2 0 1 V ns Clock Fall Time peak to peak tCHCL 2 0 1 V ns CS Active Setup Time relative to CLK tSLCH tCSS 5 ns CS Not Active Hold Time relati...

Page 97: ...to reset the device tRESET 2 1 5 s Write Status Register Time tW 10 15 ms Byte Program Time First Byte 4 tBP1 30 50 s Additional Byte Program Time After First Byte 4 tBP2 2 5 12 s Page Program Time tP...

Page 98: ...tCLH MSB OUT 9 9 Serial Input Timing CS CLK IO input tCHSL MSB IN tSLCH tDVCH tCHDX tSHCH tCHSH tCLCH tCHCL LSB IN tSHSL 9 10 HOLD Timing CS CLK IO output HOLD tCHHL tHLCH tCHHH tHHCH tHLQZ tHHQX IO...

Page 99: ...ers Inches Min Nom Max Min Nom Max A 0 70 0 75 0 80 0 028 0 030 0 031 A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 35 0 40 0 48 0 014 0 016 0 019 C 0 20 REF 0 008 REF D 7 90 8 00 8 10 0 311 0 315 0 319 D2...

Page 100: ...tions I Industrial 40 C to 85 C E 8 pad WSON 8x6mm V 2 7V to 3 6V 256F 256M bit 25Q SpiFlash Serial Flash Memory with 4KB sectors Dual Quad I O W Winbond Notes 1 The W prefix and the Temperature desig...

Page 101: ...umbers for the W25Q256FV SpiFlash Memory Please contact Winbond for specific availability by density and package type Winbond SpiFlash memories use a 12 digit Product Number for ordering However due t...

Page 102: ...of their respective owner Important Notice Winbond products are not designed intended authorized or warranted for use as components in systems or equipment intended for surgical implantation atomic e...

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