FOR MOBILE APPLICATIONS
W25Q256FV
Publication Release Date: May 13, 2012
- 52 - Preliminary - Revision M1
M7-0
*
/CS
CLK
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 19c. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)”
instruction to accommodate a wide range of applications with different needs for either maximum Fast
Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy
clocks upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-
0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous
Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 8.2.45 for details.
Figure 24c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4
≠
10, QPI Mode)
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Mode 0
Mode 3
0
1
IO
0
IO
1
IO
2
IO
3
EBh
2
3
4
5
20
16
12
8
21
17
22
18
23
19
13
9
14
10
15
11
A23-16
6
7
8
9
10
4
0
5
1
6
2
7
3
A15-8
A7-0
Byte 1
Byte 2
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
4
0
5
1
6
2
7
3
11
12
13
14
4
5
6
7
IOs switch from
Input to Output
Byte 3
Instruction
*
"Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
