5.3 Addressing
5.3.1 Overview
To provide specific addressing of the installed peripheral modules,
certain addresses must be allocated in the CPU. At the start-up of the
CPU, this assigns automatically peripheral addresses for digital in-/
output modules starting with 0 and ascending depending on the slot
location. If no hardware project engineering is available, the CPU
stores at the addressing analog modules to even addresses starting
with 256.
5.3.2 Addressing Backplane bus I/O devices
The CPU 312-5BE13 provides an I/O area (address 0 ... 8191) and a
process image of the In- and Outputs (each address 0 ... 127). The
process image stores the signal states of the lower address (0 ... 127)
additionally in a separate memory area.
The process image this divided into two parts:
n
process image to the inputs (PII)
n
process image to the outputs (PIQ)
The process image is updated automatically when a cycle has been
completed.
Maximally 8 modules may be addressed by the CPU 312-5BE13. The
extension by means of extension racks is not possible.
You may access the modules with read res. write accesses to the
peripheral bytes or the process image. To define addresses a hard-
ware configuration may be used. For this, click on the properties of
the according module and set the wanted address.
If you do not like to use a hardware configuration, an automatic
addressing comes into force. At the automatic address allocation
DIOs occupy depending on the slot location always 4byte and AIOs,
FMs, CPs always 16byte at the bus. Depending on the slot location
the start address from where on the according module is stored in the
address range is calculated with the following formulas:
n
DIOs: Start address = 4×(slot -4)
n
AIOs, FMs, CPs: Start address = 16×(slot -4)+256
Max. number of plug-
gable modules
Define addresses by
hardware configuration
Automatic addressing
VIPA System 300S
Deployment CPU 312-5BE13
Addressing > Addressing Backplane bus I/O devices
HB140 | CPU-SC | 312-5BE13 | GB | 15-50
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