Manual VIPA CPU 21x
Chapter 11 Integrated OBs SFBs SFCs
HB103E - Rev. 05/45
11-39
Order ready with errors
Set:
Per plug-in: when the according order has been
commissioned with errors. Error causes are to find
encrypted in the high-part of the indicator word.
Delete:
Per plug-in: when the according order is triggered for a
second time.
Analyze:
Per user: to proof that the order has been commissioned
with errors. If set, the error causes are to find in the high-
byte of the indicator word.
Here you may check if the data transfer is still running or if the data fetch
res. transmission is already finished. By means of the bit "Enable/Disable"
you may block the data transfer for this order (Disable=1; Enable=0).
Data fetch / Data transmission is active
Set:
Per handling block SEND or RECEIVE, if the
fetch/transmission has been started, e.g. when data is
transferred with the ALL-function (DMA-replacement), but
the impulse came per SEND-DIRECT.
Delete:
Per handling blocks SEND or RECEIVE, if the data
transfer of an order is finished (last data block has been
transferred).
Analyze:
Per user: During the data transfer CP << >>AG the user
must not change the record set of an order. This is
uncritical with PRIO 0/1 orders, because here the data
transfer is realizable in one block cycle. Larger data
amounts however are transferred in blocks during more
AG cycles. To ensure data consistency you should proof
that the data block isn’t in transfer any more before you
change the content!
Data transmission is active
Set:
Per handling block SEND, when the data transition for an
order is ready.
Delete:
Per handling block SEND, when the data transfer for a
new order has been started (new trigger).
Per user: When analysis is ready (flank creation).
Analyze:
Per user: Here you may ascertain, if the record set of an
order has already been transferred to the CP res. at
which time a new record set concerning a running order
(e.g. cyclic transition) may be started.
Bit 3
Data management
Byte 1,
Bit 4 to Bit 7
Bit 4
BIT 5
Summary of Contents for CPU 21 Series
Page 1: ...Manual VIPA CPU 21x Order No VIPA HB103E Rev 05 45 ...
Page 2: ...Lerrzeichen ...
Page 6: ...About this Manual Manual VIPA CPU 21x Subject to change to cater for technical progress ...
Page 10: ...Contents Manual VIPA CPU 21x iv HB103E Rev 05 45 ...
Page 30: ...Chapter 1 Principles Manual VIPA CPU 21x 1 18 HB103E Rev 05 45 ...
Page 58: ...Chapter 2 Hardware description Manual VIPA CPU 21x 2 28 HB103E Rev 05 45 ...
Page 80: ...Chapter 3 Deployment CPU 21x Manual VIPA CPU 21x 3 22 HB103E Rev 05 45 ...
Page 178: ...Chapter 5 Deployment CPU 21x 2BT02 with H1 TCP IP Manual VIPA CPU 21x 5 48 HB103E Rev 05 45 ...
