VIPA CPU 21 Series, Manual

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Chapter 12 Instruction list Manual VIPA CPU 21x
12-36 HB103E - Rev. 05/45
Event-ID Description
0xE003 Error at periphery-access
Additional info 1: periphery-address
Additional info 2: slot
Additional info 3: irrelevant
0xE004 Periphery-address twice used
Additional info 1: periphery-address
Additional info 2: slot
Additional info 3: irrelevant
0xE005 Error at parsing of address information (SDB2000 / SDB1)
0xE006 Error at parsing of DP slave information (SDB2000)
0xE007 Configured in-/output bytes do not fit in the peripheral area
(DP slave / High-speed counter)
0xE008 Error at parsing of HighSpeedCounter information
(SDB2000)
0xE009 Error at backplane bus access (no Ready / EMV)
0xE010 Not defined module detected at backplane bus
Additional info 1: irrelevant
Additional info 2: slot
Additional info 3: type
0xE011 Masterproject is not possible at Slave CPU or error on slave
configuration
0xE012 Error at parametrization / configuration backplane bus
0xE013 Error at access shiftregistermode to digital module
0xE014 Error at Check_Sys
0xE015 Error at access master
Additional info 1: irrelevant
Additional info 2: slot master (32 = integrated master)
Additional info 3: irrelevant
0xE016 Max. blocksize at mastertransfer overrange
Additional info 1: periphery-address
Additional info 2: slot
Additional info 3: irrelevant
0xE017 Error at access to internal DP slave
0xE018 Error at mapping of DP master periphery
0xE019 Error at detection backplane bus
0xE01A Error at detection of mode (8/9Bit)
0xE0C0 Error not enough memory for storing block
(blocksize too big)
0xE0CC Error at communication MPI / Serial
0xE100 MMC access error
0xE101 MMC file system error
0xE102 MMC FAT error
0xE104 MMC error at saving
0xE200 MMC writing ready (Copy Ram2Rom)
0xE210 MMC reading ready (Loading project after reset)
0xE300 Internal Flash writing ready (Copy Ram2Rom)
Overview of the
Event-Ids