VIPA CPU 21 Series, Manual

Page: 342 / 394

Chapter 11 Integrated OBs SFBs SFCs Manual VIPA CPU 21x
11-40 HB103E - Rev. 05/45
Data fetch active
Set: Per RECEIVE, when data fetch for a new order has been
finished.
Delete: Per RECEIVE, when data transfer to AG for a new order
(new trigger) has been started. Per user, when analyzing
(edge creation).
Analyze: Per user: Here you may ascertain, if the record set of an
order has already been transferred to the CP res. at what
time a new record set for the current order has been
transferred to the AG.
Disable/Enable data block
Set: Per user: to avoid overwriting an area by the RECEIVE
block res. data transition of an area by the SEND block
(only for the first data block).
Delete: Per user: to release the according data area.
Analyze: Per handling blocks SEND and RECEIVE: if Bit 7 is set,
there is no data transfer anymore, but the blocks
announce an error to the CP.
In the length word the handling blocks (SEND, RECEIVE) store the already
transferred data of the current order, i.e. the received data amount for
receiving orders, the sent data amount for sending orders.
Describe: Per SEND, RECEIVE during the data transfer. The length
word is calculated from:
current transfer
amount of already transferred data
Delete: Per overwrite res. with every new SEND, RECEIVE,
FETCH.
If the bit "order ready without error" res. "Data fetch/data
transition ready " is set, the "Length word" contains the
current source res. destination length.
If the bit "order ready with error" is set, the length word
contains the data amount transferred before the failure
occurred.
Bit 6
Bit 7
Length word
Byte 2 and Byte 3