VIPA CPU 21 Series, Manual

Page: 361 / 394

Manual VIPA CPU 21x Chapter 12 Instruction list
HB103E - Rev. 05/45 12-7
Registers
The ACCUs are registers for the processing of Byte, words or double
words. Therefore the operands are loaded in the ACCUs and combined.
The result of the instruction is always in ACCU1.
ACCU Bit
ACCUx (x=1 to 2) Bit 0 to Bit 31
ACCUx-L Bit 0 to Bit 15
ACCUx-H Bit 16 to Bit 31
ACCUx-LL Bit 0 to Bit 7
ACCUx-LH Bit 8 to Bit 15
ACCUx-HL Bit 16 to Bit 23
ACCUx-HH Bit 24 to Bit 31
The address registers contain the area-internal or area-crossing addresses
for the register-indirect addressed instructions. The address registers are
32Bit wide.
The area-internal or area-crossing addresses have the following structure:
area-internal address:
00000000 00000bbb bbbbbbbb bbbbbxxx
area-crossing address:
10000yyy 00000bbb bbbbbbbb bbbbbxxx
Legend: b Byte address
x Bit number
Y Range ID
(see chapter "Addressing examples")
ACCU1 and
ACCU2 (32Bit)
Address register
AR1 and AR2
(32Bit)