EBX-41 Reference Manual
62
Appendix B
– Custom Programming
PLD Interrupts
The PLD can generate interrupts for the internal 8254 timers and the external SPI interrupt
(which includes the DIO device interrupt). The SPI interrupt settings are discussed in the section
on “SPX Expansion Bus.” This section covers the interrupt settings for the 8254 timers.
I
NTERRUPT
C
ONTROL
R
EGISTER
This register enables interrupts.
IRQCTRL (Read/Write) CA3h
D7
D6
D5
D4
D3
D2
D1
D0
IRQEN
IRQSEL2
IRQSEL1
IRQSEL0
reserved
IMSK_TC5
IMSK_TC4
IMSK_TC3
Table 31: Interrupt Control Register Bit Assignments
Bit
Mnemonic
Description
D7
IRQEN
IRQ Enable
— Enables or disables an interrupt.
0 = Disable interrupt
1 = Enable interrupt
D6-D5
IRQSEL(2:0)
Specifies the interrupt mapping (this setting is ignored when IRQEN = 0 …
interrupts are disabled):
"000"
IRQ3 (default)
"001"
IRQ4
"010"
IRQ5
"011"
IRQ10
"100"
IRQ6
"101"
IRQ7
"110"
IRQ9
"111"
IRQ11
D4
Reserved
These bits are reserved. Only write 0 to these bits and ignore all read values.
D2
IMASK_TC5
Mask for the 8254 Timer #5 output (terminal count) Interrupt.
0 = Disable interrupt
1 = Enable interrupt
D1
IMASK_TC4
Mask for the 8254 Timer #4 output (terminal count) Interrupt.
0 = Disable interrupt
1 = Enable interrupt
D0
IMASK_TC3
Mask for the 8254 Timer #3 output (terminal count) Interrupt.
0 = Disable interrupt
1 = Enable interrupt
Note
: IRQ3, IRQ4, IRQ5, IRQ10 are also defined for the SPX interface interrupts. If one of these interrupts
is selected for the SPX interface and also enabled here for the timer interrupts, then the interrupt sources
are combined (i.e., logically OR’d).
B
B
