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VersaLogic Copperhead VL-EBX-41, Reference Manual

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VersaLogic Copperhead VL-EBX-41 Reference Manual Download Page 45

Interfaces and Connectors 

EBX-41 Reference Manual 

39

 

6.

 

Write the analog output channel number (0 to 3) to Bits 3-0 and the write-and-update-
channel command 3h to Bits 7-4 of SPIDATA3 (I/O address CADh) – Any write 
operation to this register triggers an SPI transaction. For example, if writing to the third 
DAC channel (channel number 2) the value written to SPIDATA3 is 32h.

 

7.

 

Poll the SPI BUSY bit in the SPISTATUS register until the conversion is completed.

 

8.

 

The D/A output will be stable in no more than 5 µs. 

Summary of Contents for Copperhead VL-EBX-41

Page 1: ...ence Manual DOC REV 7 25 2014 Copperhead VL EBX 41 Intel 3rd Generation Core Quad or Dual Core SBC with Ethernet HD Graphics ACPI 4 0 SATA RAID USB eUSB mSATA SUMIT HD Audio Serial Analog Digital I O and SPX ...

Page 2: ...ry effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligation to notify anyone of such changes ...

Page 3: ...information and resources for this product including Reference Manual PDF format Operating system information and software drivers Data sheets and manufacturers links for chips used in this product Photograph of the circuit board BIOS information and upgrades The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your VersaLogic product VersaTech KnowledgeBase ...

Page 4: ...OS Setup 9 Operating System Installation 9 Physical Details 10 Dimensions and Mounting 10 Hardware Assembly 14 Standoff Locations 14 External Connectors 15 VL EBX 41 Connector Locations Top 15 VL EBX 41 Connector Locations Bottom 16 VL EBX 41 Connector Functions and Interface Cables 17 VL CBR 5013 Connector Locations 18 VL CBR 5013 Connector Functions 19 VL CBR 4004 Connector Locations 19 Jumper B...

Page 5: ...eUSB 32 Ethernet 32 Ethernet Connectors 32 Status LED 33 USB 34 Serial Ports 34 COM Port Configuration 34 Serial Port Connectors 35 Analog Input 36 External Connections 36 Analog Input Using the SPI Interface 37 Analog Output 38 Digital I O 40 Digital I O Port Configuration Using the SPI Interface 41 Audio 45 Counter Timers 46 PCIe Mini Card mSATA 46 PCIe Mini Card Wireless Status LEDs 48 User I O...

Page 6: ...Code Register 58 PLD Revision and Type Register 59 BIOS and Jumper Status Register 60 Appendix A References 61 Appendix B Custom Programming 62 PLD Interrupts 62 Interrupt Control Register 62 Interrupt Status Register 63 8254 Timer Control Register 64 Miscellaneous Control Register 66 A D and D A Control Status Register 67 ...

Page 7: ...n for on board security SPX interface supports up to four external SPI devices either of user design or any of the SPX series of expansion boards with clock frequencies from 1 8 MHz Intel High Definition Audio HDA compatible Stereo line in and line out PCIe 104 Type 1 or SUMIT expansion EBX standard 5 75 x 8 00 footprint Field upgradeable BIOS with OEM enhancements Customization available The Copp...

Page 8: ... device interface One mSATA socket One PCIe Mini Card mSATA socket Ethernet Interface Two Intel 82574IT based 10BaseT 100BaseTX 1000BaseT Ethernet Controllers Analog Input 16 channel 12 bit single ended 100 Ksps channel independent input range bipolar 5 10 or unipolar 0 to 5V or 0 to 10V Analog Output 8 channel 12 bit single ended 100 Ksps 0 to 4 096V Serial Interface COM Ports Four RS 232 422 por...

Page 9: ...Introduction EBX 41 Reference Manual 3 Copperhead Block Diagram Figure 1 VL EBX 41 Block Diagram ...

Page 10: ... CPUs in the event of this occurrence MODEL DIFFERENCES VersaLogic offers both commercial and industrial temperature models of the VL EBX 41 The basic operating temperature specification for Copperhead models is shown below Thermal Solution Temp Range Airflow Heat plate 0 C to 60 C Zero airflow 40 C to 85 C 125 Linear Feet per Minute 0 5 Linear Meters per Second Heat sink fanless 0 C to 60 C 125 L...

Page 11: ...Y Warning To prevent shorting premature failure or damage to the lithium battery do not place the board on a conductive surface such as metal black conductive foam or the outside surface of a metalized ESD protective pouch The lithium battery may explode if mistreated Do not recharge disassemble or dispose of in fire Dispose of used batteries promptly and in an environmentally suitable manner HAND...

Page 12: ... by calling 503 747 2261 Please provide the following information Your name the name of your company your phone number and e mail address The name of a technician or engineer that can be contacted if any questions arise Quantity of items being returned The model and serial number barcode of each item see Figure 8 for location A detailed description of the problem Steps you have taken to resolve or...

Page 13: ...installation CD Basic Setup The following steps outline the procedure for setting up a typical development system The VL EBX 41 should be handled at an ESD workstation or while wearing a grounded antistatic wrist strap Before you begin unpack the VL EBX 41 and accessories Verify that you received all the items you ordered Inspect the system visually for any damage that may have occurred in shippin...

Page 14: ... to the display Plug the USB CD ROM drive keyboard and mouse into on board USB ports J12 J13 J15 or J16 Plug the SATA data cable VL CBR 0701 into a SATA socket J3 J5 J7 or J9 and attach the SATA hard drive to the cable Attach the ATX SATA power cable VL CBR 0401 to the ATX power supply and to the SATA hard drive OS Installation CD ROM J18 VL EBX 41 Copperhead USB Keyboard and Mouse ATX Power Suppl...

Page 15: ...rt the OS installation CD in the CD ROM drive and select to boot from the CD ROM drive 7 Install Operating System Install the operating system according to the instructions provided by the OS manufacturer See Operating System Installation Note If you intend to operate the VL EBX 41 under Windows XP or Windows XP Embedded be sure to use Service Pack 3 SP3 and all updates for full support of the lat...

Page 16: ...tandards which provide for specific mounting hole and PCIe 104 stack locations as shown in the diagram below Figure 3 VL EBX 41 Dimensions and Mounting Holes Not to scale All dimensions in inches 3 0 20 0 00 0 20 1 87 5 0 00 5 80 2 65 5 25 5 35 5 55 7 80 7 60 5 70 2 80 0 125 DIA x8 Use 3 mm or 4 standoffs ...

Page 17: ... prevent excessive flexing when expansion modules are mated and de mated Flex damage caused by excessive force on an improperly mounted circuit board is not covered under the product warranty Figure 4 VL CBR 5013 Dimensions and Mounting Holes Not to scale All dimensions in inches 1 95 1 57 5 50 5 10 1 17 1 24 0 065 ...

Page 18: ...ical Details EBX 41 Reference Manual 12 Figure 5 VL CBR 4004 Dimensions and Mounting Holes Not to scale All dimensions in inches J1 J2 J3 J4 J6 J7 J8 J9 J5 2 38 2 87 0 25 0 25 0 40 1 95 0 70 0 63 0 62 0 06 ...

Page 19: ...X 41 Reference Manual 13 Figure 6 Heat Plate Dimensions and Mounting Holes Not to scale All dimensions in millimeters 3 20 3 20 44 48 56 00 89 00 PEM TSOS M25 600 4X 2 0mm Drill 2X M2 5 x 0 45mm 2X 30 00 11 00 8 00 33 00 ...

Page 20: ... as mounting struts for the expansion stack The entire assembly can sit on a table top or be secured to a base plate When bolting the unit down make sure to secure all eight standoffs A and B to the mounting surface to prevent circuit board flexing An extractor tool is available part number VL HDW 203 to separate expansion modules from the stack Note Standoffs and screws are available as part numb...

Page 21: ...J2 DDR3 SO DIMM B J4 CPU Fan J5 SATA 3 J9 SATA 2 J3 SATA 0 J7 SATA 1 J5 J9 J3 J7 J6 PCIe 104 J8 PCIe Mini Card mSATA J11 mSATA J10 SUMIT B J14 SUMIT A J12 USB 1 J13 USB 0 J15 USB 3 J16 USB 2 J19 Analog I O Timers J21 DIO J22 Ethernet LED J28 SPX J29 User I O J26 DisplayPort C J27 DisplayPort D J26 J27 J15 J16 J12 J13 Heat Plate Heatsink Fan Pin 1 798375 M o d e l XXXXX Serial Number Model Number ...

Page 22: ...Physical Details EBX 41 Reference Manual 16 VL EBX 41 CONNECTOR LOCATIONS BOTTOM Figure 9 VL EBX 41 Connector Locations Bottom J33 DDR3 SO DIMM A J36 2 mm eUSB Flash Port J32 LVDS ...

Page 23: ...d SATA VL CBR 0702 VL CBR 0401 20 SATA data latching ATX to SATA power adapter 30 J10 SUMIT B Top Samtec ASP 129646 01 25 J11 mSATA 30 J12 USB1 3 0 Standard USB Type A 34 J13 USB0 3 0 Standard USB Type A 34 J14 SUMIT A Top Samtec ASP 129646 01 25 J15 USB3 2 0 Standard USB Type A 34 J16 USB2 2 0 Standard USB Type A 34 J18 Main Power Input Molex 39 01 2080 Molex 39 00 0181 8 ea VL CBR 0808 12 ATX12 ...

Page 24: ...5 are for factory use only 2 The PCB origin is the mounting hole to the lower left as shown in Figure 3 lower right when viewing bottom side of board 3 Connectors J32 J34 and J35 are on the bottom of the board VL CBR 5013 CONNECTOR LOCATIONS Figure 10 VL CBR 5013 Connectors J7 USB1 Top USB2 Bottom J3 Audio In Top Out Bottom S1 Power D1 Programmable LED Top Power LED Bottom S2 Reset J1 USB3 Top USB...

Page 25: ...J5 COM2 Conta Clip 10250 4 5 pin screw terminal J6 COM3 Conta Clip 10250 4 5 pin screw terminal J7 USB1 USB2 USB Type A USB Host J8 External Reset and Power Buttons Conta Clip 10250 4 3 pin screw terminal D1 PLED Top Power LED Bottom LED S1 Power Button Pushbutton S2 Reset Button Pushbutton SP1 Speaker Piezo speaker VL CBR 4004 CONNECTOR LOCATIONS Figure 11 VL CBR 4004 Connectors The VL CBR 4004 c...

Page 26: ...Physical Details EBX 41 Reference Manual 20 Jumper Blocks JUMPERS AS SHIPPED CONFIGURATION Figure 12 Jumper Block Locations V1 V7 V2 V3 V4 V6 1 3 5 7 2 4 6 8 1 1 3 1 2 2 4 2 1 2 3 2 1 ...

Page 27: ...34 V3 CMOS RAM and Real time Clock Erase 1 2 In Normal 2 3 In Erase CMOS RAM and real time clock Note Whenever CMOS RAM is cleared it is good practice to clear NVRAM using jumper V1 1 2 at the same time 1 2 In 24 V4 BIOS Force Recovery In Enable Out Disable Out V5 Jumper block not installed V6 1 2 System BIOS Selector In Primary system BIOS selected Out Secondary system BIOS selected The Primary s...

Page 28: ...ion slots 12V 5Vsee note and 3 3V is not provided by voltage regulators on the Copperhead circuit board These voltages if needed must be provided externally by the user The Copperhead circuit board passes the voltages from connector J18 to the expansion slots Note Up to 4A 5V is provided from an on board supply If additional amperage is needed 8 4A max an external supply must be used The exact pow...

Page 29: ...mature failure or damage to the lithium battery do not place the board on a conductive surface such as metal black conductive foam or the outside surface of a metalized ESD protective pouch The lithium battery may explode if mistreated Do not recharge disassemble or dispose of in fire Dispose of used batteries promptly Normal battery voltage should be at least 3 0V If the voltage drops below 3 0V ...

Page 30: ...l not boot if you do not remove this jumper 6 Power on the Copperhead Note Whenever NVRAM cleared it is good practice to clear CMOS RAM using Jumper V3 at the same time CMOS RAM CLEARING CMOS RAM AND RTC A jumper may be installed into V3 2 3 to erase the contents of the CMOS RAM and the Real Time Clock When clearing CMOS RAM 1 Power off the Copperhead 2 Remove the jumper from V3 1 2 install it on ...

Page 31: ...MB I2C_DATA SMBus data 5 3 3V 3 3V power 6 SMB I2C_CLK SMBus clock 7 NC Not connected 8 SMB I2C_ALERT SMBus interrupt line in 9 NC Not connected 10 SPI uWire_DO SPI data out from master 11 NC Not connected 12 SPI uWire_DI SPI data in to master 13 NC Not connected 14 SPI uWire_CLK SPI clock 15 5V 5V power 16 SPI uWire_CS0 SPI chip select 0 17 USB3 USB3 data 18 SPI uWire_CS1 SPI chip select 1 19 USB...

Page 32: ...17 C_PETn0 PCIe link C lane 0 transmit 18 C_PERn0 PCIe link C lane 0 receive 19 GND Ground 20 GND Ground 21 C_PETp1 PCIe link C lane 1 transmit 22 C_PRTp1 PCIe link C lane 1 transmit 23 C_PETn1 PCIe link C lane 1 transmit 24 C_PERn1 PCIe link C lane 1 transmit 25 GND Ground 26 GND Ground 27 NC Not connected 28 NC Not connected 29 NC Not connected 30 NC Not connected 31 GND Ground 32 GND Ground 33 ...

Page 33: ... Copperhead is booted the BIOS tests for a video monitor attached to the VGA port If a monitor is not detected during this test the VGA signals are disabled Table 7 VGA Video Output Pinout J1 Pin Signal Name Function Mini DB15 Pin 1 GND Ground 6 2 RED Red Video 1 3 GND Ground 7 4 GREEN Green Video 2 5 GND Ground 8 6 BLUE Blue Video 3 7 GND Ground 5 8 HSYNC Horizontal Sync 13 9 GND Ground 10 10 VSY...

Page 34: ...rovided to pins 19 and 20 of J32 is protected by a software controllable power switch 1 Amp max This switch is controlled by the L_VDD_EN signal from the LVDS interface controller in the Intel 7 Series Platform Controller Hub PCH See the Intel GM45 Datasheet for detailed information MINI DISPLAYPORT Two DisplayPorts are provided using two 20 pin mini DisplayPort connectors at locations J26 and J27...

Page 35: ...Setup and some operating systems such as DOS can use this console for user interaction Console redirection settings are configured on the Serial Port Console Redirection submenu of the Advanced tab It is disabled by default When enabled the console will be available both at the serial port and using the standard keyboard video console The video console may resize and slow down to accommodate the s...

Page 36: ...types of power connectors If the power supply you are using does not provide SATA connectors adapters are available Table 10 SATA Port Pinout SATA Pin Signal Name Function 1 GND Ground 2 TX Transmit 3 TX Transmit 4 GND Ground 5 RX Receive 6 RX Receive 7 GND Ground mSATA The Copperhead provides one mSATA only slot at connector J11 J11 Pin Signal Name Function 1 Reserved Not connected 2 3 3V 3 3V so...

Page 37: ... A Host transmitter diff pair 32 Two Wire I F Two wire I F data 33 A Host transmitter diff pair 34 GND Ground 35 GND Ground 36 Reserved Not connected 37 GND Ground 38 Reserved Not connected 39 3 3V 3 3V source 40 GND Ground 41 3 3V 3 3V source 42 Reserved Not connected 43 GND NC Ground Not connected 3 44 Reserved Not connected 45 Vendor Not connected 46 Reserved Not connected 47 Vendor Not connect...

Page 38: ...on D9 lights with activity on the eUSB port if supported by the eUSB module Ethernet The Copperhead features two on board Intel 82574IT Gigabit Ethernet controllers The controllers provide a standard IEEE 802 3 Ethernet interface for 1000Base T 100Base TX and 10Base T applications RJ45 connectors are located at locations J25 Ethernet 0 and J24 Ethernet 1 While these controllers are not NE2000 comp...

Page 39: ...ply 2 YEL0 Yellow LED Ethernet 0 3 ORN0 Orange LED Ethernet 0 4 GRN0 Green LED Ethernet 0 5 3 3V Protected Power Supply 6 YEL1 Yellow LED Ethernet 1 7 ORN1 Orange LED Ethernet 1 8 GRN1 Green LED Ethernet 1 9 GND Ground 10 W_DISABLE PCIe Mini Card Disable W_Disable Signal The W_DISABLE is for use with optional wireless PCIe Mini Cards The signal allows you to disable a wireless card s radio operati...

Page 40: ... Connector 4 CRB 5013 paddle board Type A Connector 5 CRB 5013 paddle board Type A Connector 6 CRB 5013 paddle board Type A Connector 7 CRB 5013 paddle board Type A Connector 8 SUMIT 9 SUMIT 10 SUMIT PCIe 104 11 SUMIT PCIe 104 12 eUSB Module 13 PCIe Mini Card mSATA Serial Ports The Copperhead features four on board 16550 based serial communications channels located at standard PC I O addresses All...

Page 41: ...EC 61000 4 2 rated TVS components to help protect against ESD damage Table 15 COM0 1 Pinout VL CBR 5013 Connector J2 COM0 COM1 Top DB9 J2 Pin Bottom DB9 J2 Pin RS 232 RS 422 1 1 2 2 RXD RxD 3 3 TXD TxD 4 4 5 5 Ground Ground 6 6 7 7 RTS TxD 8 8 CTS RxD 9 9 Table 16 COM2 3 Pinout VL CBR 5013 Connectors J5 6 COM2 COM3 J5 Pin J6 Pin RS 232 RS 422 1 1 Ground Ground 2 2 RXD RxD 3 3 CTS RxD 4 4 TXD TxD 5...

Page 42: ...ng of ADIOMODE See SPI Registers for a complete description of the registers See the Linear Technology LTC1857 A D Converter Datasheet for programming information Warning Application of analog voltages greater than 25V or less than 25V can damage the converter EXTERNAL CONNECTIONS Single ended analog voltages are applied to connector J19 as shown in the following table Standard VL EBX 41 models in...

Page 43: ...bits 5 4 and a 2 bit input range code to bits 3 2 of SPIDATA3 I O address CADh Any write operation to this register triggers an SPI transaction The 2 bit input range codes are 0 5V 1 10V 2 0 to 5V or 3 0 to 10V Bit 7 must be set to a 1 for a single ended channel fyi each A D can be configured for either 8 single ended inputs or 4 differential inputs For example if converting the 4th A D channel ch...

Page 44: ... IO19 24 Analog Output 4 4 IO20 25 Ground 5 GND3 PBRST 26 Analog Output 5 J7 1 IO21 27 Analog Output 6 Analog Output 2 IO22 28 Analog Output 7 Custom 3 IO23 29 Analog Output 8 4 IO24 30 Ground 5 GND3 Contact Sales VersaLogic com for information on custom orders Analog Output Using the SPI Interface The following procedure can be used to set an analog output using the SPI interface 1 Set ADIOMODE 1...

Page 45: ...and 3h to Bits 7 4 of SPIDATA3 I O address CADh Any write operation to this register triggers an SPI transaction For example if writing to the third DAC channel channel number 2 the value written to SPIDATA3 is 32h 7 Poll the SPI BUSY bit in the SPISTATUS register until the conversion is completed 8 The D A output will be stable in no more than 5 µs ...

Page 46: ...CBR 4004 Pin Silkscreen 1 Digital I O 1 J1 5 IO1 2 Digital I O 2 4 IO2 3 Digital I O 3 3 IO3 4 Digital I O 4 2 IO4 5 Ground 1 GND1 6 Digital I O 5 J2 5 IO5 7 Digital I O 6 4 IO6 8 Digital I O 7 3 IO7 9 Digital I O 8 2 IO8 10 Ground 1 GND1 11 Digital I O 9 J3 5 IO9 12 Digital I O 10 4 IO10 13 Digital I O 11 3 IO11 14 Digital I O 12 2 IO12 15 Ground 1 GND2 16 Digital I O 13 J4 5 IO13 17 Digital I O ...

Page 47: ... CA8h MOV AL 26h SPICONTROL SPI Mode 00 24bit auto SPI 6 OUT DX AL MOV DX CA9h MOV AL 30h SPISTATUS 8MHz no IRQ left shift OUT DX AL MOV DX CABh MOV AL 08h SPIDATA1 Set HAEN Bit to a 1 OUT DX AL MOV DX CACh MOV AL 0Ah SPIDATA2 MCP23S17 IOCON addr 0x0A OUT DX AL MOV DX CADh MOV AL 40h SPIDATA3 MCP23S17 write to device 000 OUT DX AL BUSY MOV DX CA9h IN AL DX Get SPI status AND AL 01h Isolate the BUS...

Page 48: ...irror Open Drain interrupts OUT DX AL MOV DX CACh MOV AL 0Ah SPIDATA2 MCP23S17 address 0x0A OUT DX AL MOV DX CADh MOV AL 40h SPIDATA3 MCP23S17 write command OUT DX AL Writing to a Digital I O Port Using the SPI Interface The following code example initiates a write of 55h to Digital I O port bits DIO15 DIO8 Write 44h to configure MCP23S17 register IOCON MOV DX CA8h MOV AL 26h SPICONTROL SPI Mode 0...

Page 49: ...ND AL 01h Isolate the BUSY flag JNZ BUSY Loop if SPI transaction not complete Reading a Digital I O Port Using the SPI Interface The following code example reads the DIO15 DIO8 input lines REGISTER ASSIGNMENT CONST SPICONTROL1 HCA8 CONST SPICONTROL2 HCA9 CONST SPISTATUS HCA9 CONST SPIDATA1 HCAB CONST SPIDATA2 HCAC CONST SPIDATA3 HCAD INITIALIZE SPI CONTROLLER SPICONTROL1 Register D7 CPOL 0 SPI Clo...

Page 50: ...R 1 D0 0 0 This bit has no function OUT SPIDATA1 H44 MCP23S17 IOCON Register Address OUT SPIDATA2 HA MCP23S17 SPI Control Byte Write D7 SLAVEFA3 0 Slave Address Fixed Portion D6 SLAVEFA2 1 D5 SLAVEFA1 0 D4 SLAVEFA0 0 D3 SLAVEHA2 0 Slave Address Bits Hardware Address Bits D2 SLAVEHA1 0 D1 SLAVEHA0 0 D0 READWRITE 0 Read Write Bit Write OUT SPIDATA3 H40 WHILE INP SPISTATUS AND H1 H1 WEND INITIALIZE D...

Page 51: ...ge The J29 main I O connector provides the line level stereo input and line level stereo output connection points The outputs will drive most amplified PC speaker sets The following table shows the pinout of the audio connector J3 on the VL CBR 5013 breakout board Table 20 VL CBR 5013 J3 Audio Connector Pinout J3 Pin Signal Name Function 1 LINE_INL Line In Left 2 LINE_INR Line In Right 3 HDA_GND H...

Page 52: ...CA3h Interrupt Control Register IRQSTAT R Status Write Clear CA4h Interrupt Status Register TMCNTRL R W CA5h Timer Control Register TIMBASEMS R W CA6h Timer Base MS Address Register TIMBASELS R W CA7h Timer Base LS Address Register PCIe Mini Card mSATA The socket at location J8 accepts a full height PCI Express Mini Card or an mSATA module The PCIe Mini Card interface includes one PCIe x1 lane one...

Page 53: ...ot connected 20 W_DISABLE Wireless disable 1 Reserved Not connected 21 GND Ground GND Ground 22 PERST Card reset Reserved Not connected 23 PERn0 PCIe receive B Host receiver diff pair 24 3 3VAUX 3 3V auxiliary source 3 3V 3 3V source 25 PERp0 PCIe receive B Host receiver diff pair 26 GND Ground GND Ground 27 GND Ground GND Ground 28 1 5V 1 5V power 1 5V 1 5V power 29 GND Ground GND Ground 30 SMB_C...

Page 54: ...lable as an option on custom boards 3 This pin is not grounded on the Copperhead to make it available for mSATA module detection 4 This signal drives the blue LED activity indicator at location D11 upper right corner of the board as shown in Figure 6 This LED lights with mSATA disk activity if supported by the mSATA module 5 Some PCIe modules use this signal as a second Mini Card wireless disable ...

Page 55: ...6 7 5 0V 10 Ground Ground 35 Data 11 TXD TxD 36 Data 12 RTS TxD 37 5 0V Protected 13 COM2 Ground Ground 38 D1 Programmable LED 14 J5 RXD RxD 39 SP1 Speaker 15 CTS RxD 40 S2 J8 Pin 1 Pushbutton Reset 16 Ground Ground 41 S1 J8 Pin 3 Power Button 17 TXD TxD 42 Ground 18 RTS TxD 43 Audio In Audio In Left 19 COM3 Ground Ground 44 J3 Top HDA ground isolated 20 J6 RXD RxD 45 Audio In Right 21 CTS RxD 46 ...

Page 56: ...in capable of sinking 1 mA The input must be driven to a voltage between 0V and 500mV to be recognized by the Copperhead Do not add an external pull up resistor to this signal This connector uses IEC 61000 4 2 rated TVS components to help protect against ESD damage A reset button is provided on the VL CBR 5013 breakout board Terminal block J8 on the breakout board also provides a reset signal on p...

Page 57: ...ation or Suspend to Disk All content of main memory is saved to non volatile memory such as a hard drive and is powered down S5 G2 Soft Off Almost the same as G3 Mechanical Off except that the power supply still provides power at a minimum to the power button to allow return to S0 A full reboot is required No previous content is retained Other components may remain powered so the computer can wake...

Page 58: ...ly by the permanent Master device on board The others are Data In and Data Out with respect to the Master The SPX implementation adds additional features such as chip selects and an interrupt input to the Master The Master device initiates all SPI transactions A slave device responds when its Chip Select is asserted and it receives Clock pulses from the Master The SPI clock rate can be software co...

Page 59: ... CPHA SPI Clock Phase Sets the SCLK edge on which valid data will be read 0 Data read on rising edge 1 Data read on falling edge D5 D4 SPILEN 1 0 SPI Frame Length Sets the SPI frame length This selection works in manual and auto slave select modes SPILEN1 SPILEN0 Frame Length 0 0 8 bit 0 1 16 bit 1 0 24 bit 1 1 32 bit D3 MAN_SS SPI Manual Slave Select Mode This bit determines whether the slave sel...

Page 60: ...e port disabled 0 0 1 SPX Slave Select 0 J28 pin 8 0 1 0 SPX Slave Select 1 J28 pin 9 0 1 1 SPX Slave Select 2 J28 pin 10 1 0 0 SPX Slave Select 3 J28 pin 11 1 0 1 A D Converter Channels 1 8 on board U34 1 1 0 Digital I O Channels 1 32 on board U22 U51 1 1 1 D A Converter Channels 1 4 on board U26 ADIOMODE 1 SS2 SS1 SS0 Slave Select 0 0 0 Same as for ADIOMODE 0 0 0 1 SUMIT SPI I F Chip Select 0 J1...

Page 61: ...RQSEL by an SPI device 0 SPI IRQ disabled default 1 SPI IRQ enabled Note The selected IRQ is shared with PC 104 ISA bus devices CMOS settings must be configured for the desired ISA IRQ D2 LSBIT_1ST SPI Shift Direction Controls the SPI shift direction of the SPIDATA registers The direction can be shifted toward the least significant bit or the most significant bit 0 SPIDATA data is left shifted MSb...

Page 62: ...d for example the LSB of a 24 bit frame would be SPIDATA1 Data is sent according to the LSBIT_1ST setting When LSBIT_1ST 0 the MSbit of SPIDATA3 is sent first and received data will be shifted into the LSbit of the selected frame size set in the SPILEN field When LSBIT_1ST 1 the LSbit of the selected frame size is sent first and the received data will be shifted into the MSbit of SPIDATA3 Data ret...

Page 63: ...Register CA2h Interrupt Control Register CA3h Interrupt Status Register CA4h 8254 Timer Control Status Register CA5h Reserved CA6h CA7h SPX Control Register CA8h SPX Status Register CA9h SPX Data Register 0 CAAh SPX Data Register 1 CABh SPX Data Register 2 CACh SPX Data Register 3 CADh Miscellaneous Control Register CAEh A D D A Control Status Register CAFh Super I O Runtime Registers C00h C80h CO...

Page 64: ...r Bit Assignments Bit Mnemonic Description D7 PLED Light Emitting Diode Controls the programmable LED on connector J29 0 Turns LED off 1 Turns LED on D6 D0 PC 6 0 Product Code These bits are hard coded to represent the product type The VL EBX 41 is uniquely identified by the code 0000101 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Product Code 0 0 0 1 1 0 0 VL EBX 41 These bits are read only 7 ...

Page 65: ... code revision PLD4 PLD3 PLD2 PLD1 PLD0 Revision 0 0 0 1 0 Rev 1 00A These bits are read only D2 TEMP Temperature Rating This bit indicates whether the VL EBX 41 is rated for standard or industrial temperature operation 0 Standard temperature operation 1 Industrial temperature operation This bit is read only D1 CUSTOM PLD Class This bit indicates whether the PLD code is standard or customized 0 St...

Page 66: ... 2 0 Jumper installed Primary system BIOS selected 1 No jumper installed Secondary system BIOS selected This bit is read only D6 BIOS_OR BIOS Jumper Override Overrides the system BIOS selector jumper and selects the BIOS with BIOS_SEL 0 No BIOS override 1 BIOS override D5 BIOS_SEL BIOS Select Selects the system BIOS when BIOS_OR is set 0 Primary BIOS selected 1 Secondary BIOS selected D4 D1 Reserv...

Page 67: ...n Intel Core Processor Family Datasheet Vol 1 Vol 2 Update Chipset Intel QM77 Platform Controller Hub Mobile Intel QM77 Express Chipset Intel BD82QM77 PCH Ethernet Controller Intel 82574IT Ethernet Controller Intel 8257IT Datasheet PCIe 104 Interface PCI 104 Express PCIe 104 Express Specification SUMIT Interface SUMIT Specification A ...

Page 68: ...able interrupt D6 D5 IRQSEL 2 0 Specifies the interrupt mapping this setting is ignored when IRQEN 0 interrupts are disabled 000 IRQ3 default 001 IRQ4 010 IRQ5 011 IRQ10 100 IRQ6 101 IRQ7 110 IRQ9 111 IRQ11 D4 Reserved These bits are reserved Only write 0 to these bits and ignore all read values D2 IMASK_TC5 Mask for the 8254 Timer 5 output terminal count Interrupt 0 Disable interrupt 1 Enable int...

Page 69: ...C4 Status for the 8254 Timer 4 output terminal count Interrupt when read 0 Timer output terminal count has not transitioned from 0 to a 1 level 1 Timer output terminal count has transitioned from a 0 to a 1 level This bit is read status and a write 1 to clear D0 ISTAT _TC3 Status for the 8254 Timer 3 output terminal count Interrupt when read 0 Timer output terminal count has not transitioned from ...

Page 70: ...er 4 input clock is 4 167 MHz internal clock PCI clock divided by 8 1 Timer 4 input clock is from User I O connector Input ICTC4 D2 TM3SEL Configure the clock source for 8254 Timer 3 0 Timer 3 input clock is 4 167 MHz internal clock PCI clock divided by 8 1 Timer 3 input clock is from User I O connector Input ICTC3 D1 D0 Reserved These bits are reserved Only write 0 to these bits and ignore all re...

Page 71: ...cade mode when the output from Timer 4 is the clock for Timer 5 The timer outputs can generate interrupts When a timer output transitions from a 0 to a 1 then an interrupt status bit is set and can generate an interrupt This bit sticks until cleared By default there are two external timer input clocks ICTC3 ICTC4 and two timer outputs OCTC3 OCTC4 on connector J19 To use all three of the 16 bit tim...

Page 72: ...Pin 51 This is only reliable for mSATA modules which drive this signal High and is not recommended 010 Use either J8 Pin 43 or J8 Pin 51 to detect mSATA modules This works on the majority of modules and is the recommended setting Note This is the BIOS default setting 011 Force the multiplexer to always be used as a PCIe Minicard 100 Force the multiplexer to always be used as an mSATA module 101 Un...

Page 73: ...ion D4 DACLDA0 This is a write only pulsed bit When a 1 is written it will strobe the LDAC signal on the LTC2634 D A Converter for channels 1 4 Writing a 0 is ignored LDAC is only used to update all 4 channels in one operation D3 ADCBUSY1 This read only status bit returns the conversion status for the LTC1857 A D for channels 9 16 0 A D is idle 1 A D is busy doing a conversion D2 ADCBUSY0 This rea...

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