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Vector
Graphic
Bitstreamer
II
Valid
oLltPIJt
data
is
present
on the
data
bus during
an output
machine
cycle Wl~en b'lerolloHing conditions are met:
The lower eight address
lines
contain
the I/O address;
SOUT
must be high, indicating an output machine
cycle;
P,'iR,
must be low, indicatir19b'ledata bus contains
valid
data.
The
appropriate signals are gated together through U8, UlS, U19, U13, and Ul7 to
produce two strobes, one for Parallel Channel A and one for Parallel Channel
B.
These
strobes
cause
the data
bus signals
to be latched by LS75 quad
latches US, U9, U16,
and U20.
These
outputs
remain
constant
until
the
particular output channel is again accessed by the CPU.
The TxRDY
and RxRDY pins on the 3251's are each connected to one of b~e
inputs of an open collector N~~D gate in Un or U10.
The other input of each
gate
comes
from one of the output
bits of t.hequad latches in
us
and U9,
which is the output
side
of Parallel
Channel
A.
Thus,
a 1 bit must
be
latched
into a specific
bit
in the output
side
of Parallel Channel A in
order for b1-}e
corresp:>ndirl3
TxRDY or RxRDY to emerge (inverted) on the other
side
of the NAND
gate.
Open
collector gates are used so that the various
interrupt signals can be "wire OR1ed" together, t.hatis, simply
wired
as a
group
to the PI~T
line,
without
blowing each other out.
The nature of an
open collector gate is that
if the output
is not low, then
it is simply
open,
and has
to be pulled
up.
PfN'T
is pulled up in b'leCPU, so that an
open (i.e. floatin:;)signal into it is treated as high by the CPU.
The
55
Hz
real time clock is created by dividing the 110 baud clock rate
signal (which is a 16 x 110 pulses/second signal) by 16, in binary
counter
U3, and then dividing
it in half
again
with
a flip-flop in U4.
Another
flip-flop in U4 then latches b'leclocl<pulse, 'rlhoseoutput
goes
to jumper
area A, pad
1.
The clock latch is reset by an input request issued by b'le
CPU to Parallel Channel 3, since
the input
enable
signal
from U17-11
is
connected to the flip-flop CLR pin U4-1.
Notice Ghat the clock latch output
is not open collector, so that as is, it cannot be \vired together
with
any
other interrupt signal.
Summary of Contents for Bitstreamer II
Page 1: ...lit t tiCAli1iC I JI U E I mAnUAL...
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Page 3: ...BITSTREAMER II BOARD Revision 1 USER S MANUAL Revision A January 1 1980...
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