Vector Graphic Bitstreamer II, User Manual, Page: 47 / 54

The heart of the serial I/O channels is the 8251 USkqT consisting of
independent receiver and tran5~itter. The function of b~e transmitter is to
accept eight bits of parallel data from the data bus, and convert this to
serial data with a wide rarl3eof formats.
The speed at vmich data is output in asynchronous mode is controlled by a
selectable clock rate derived from the 2 HHz system clock by counters U7,
U2, Ul, and VII. The clock rate is normally sixteen times the required baud
rate (though this can be chal'l3ed when the 8251 is initialized by software) ,
so a frequency of 153.6 KHz is required for 9600 baud. This gives a
frequency division ratio of 13.02, which is rounded to 13, relative to the 2
NHz clock. U7 forms a divide by 13 stage, and the gated terminal count at
V14-8 can be selected by a DIP switch for 9600 baud. The other common baud
rates, except for 110 baud, are obtained by successively dividing this
frequency in half using Ul and U1l, which are 74LS93.binary counters. The
clock frequency for 110 baud is generated by dividing the frequency for 2430
baud by 22. The desired frequency is selected by a DIP switch for each
serial channel, and applied to the TxC and RxC pins of the 8251.
The 8251 U8ART is designed to interface easily to an 8080 bus structure,
and the control signals
RB,
c/5,
C8, and WR are derived easily from ~~e
8-100 bus. Since the device was intended to be used with a bi-directional
data bus, the 8-100 split data bus is recombined as an internal data bus
using tri-state bus drivers. EIA RS-232C line drivers and receivers
interface b~e RxD and TxD output of the 8251 to the outside world. Discrete
components are used to interface with 20 mA teletype signals.
To input data, the following signal conditions must be met: The lower
eight address lines must contain the I/O address; SINP must be high,
indicating an input machine cycle is occuring; PDBIN must be high,
indicating that the data bus may be accessed by the board. The required
signals are gated together through US, VIS, Vl9, V13, and U17 to produce two
enable signals, one for Parallel Channel A and one for Parallel
Channel 3.
These enable signals strobe the input data onto the data bus at the
appropriate time using tri-state bus drivers.