United Electronic Industries PD2-MF, User Manual

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Chapter 3: Architecture
39
Clocking
The PowerDAQ board has two selectable base frequencies (11 MHz and
33 MHz) to clock acquisition. Lower frequencies are obtained by
dividing the base frequency by a 24-bit number (from 1 to 16M). To
calculate the result frequency use following formula:
Timebase = Base Frequency / (d 1)
Acquisition is clocked by two signals: conversion start (CV Start) and
channel list start (CL Start). There are four selectable sources for these
clocks:
•
Software command
•
Internal timebase
•
External clock
•
Continuous clocking (or self-retriggerable clock)
Additionally for internal or external clocks, an active edge (rising or
falling) can be selected.
Note
The PowerDAQ board will generate an error
condition each time a clock signal is applied, before
the board is ready to process it. For example, if you
clock the board with a clock frequency higher than
the rated aggregate rate, the board reports a CV/CL
start error.
The CV Start clock starts the A/D conversion. The CL Start clock starts
the channel list execution. The CV Start clocks are ignored until the CL
Start pulse is sensed. If any clock is switched to continuous clocking, it
re-triggers itself immediately after board is ready to process it.