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Chapter 3: Architecture

Channel List

The Channel List contains sequences of channels to be acquired and
their per channel gains. This sequence is known as the SCAN. The ADC

Channel List can contain 1 to 256 channel entries. Configuration data
for each channel will include the channel selection, gain, and slow bit

setting. Each Channel List block written clears and overwrites the
previous settings.

The Slow Bit is a special marker which guaranties longer settling time

for a particular channel. It is very useful when the signal is acquired has
a high (100 or 1000) gain.

The Channel list has the following format:

Bit 8

Bits 7 and 6

Bits 5 to 0

Slow bit

Gain

Channel to acquire

Table 12: Channel List Format

Gain coding
(bits 7,6)

MF PGL Gains MF PGH Gains

MFS DG-option
Gains

00 1 1 1

01 10

2 2

10 100

4 5

11 1000

8 10

Table 13: Programmable Gain Codes

Summary of Contents for PD2-MF

Page 1: ...ser Manual PowerDAQ PD2 MF and PD2 MFS PCI DAQ boards High Performance Multifunction I O boards for PCI Bus Computers October 2000 Edition Copyright 1998 2000 United Electronic Industries Inc All rights reserved ...

Page 2: ...mation furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use Contacting United Electronic Industries Address 10 Dexter Avenue Watertown Massachusetts 02472 U S A Support Telephone 617 924 1155 Fax 617 924 1441 Internet Access Support support ...

Page 3: ...n 10 Installing PowerDAQ 11 Installing the Software 12 Confirming the Installation 13 Configuring the PowerDAQ Board 14 Input Modes 14 Test Program 17 Connectors 18 Architecture 25 Functional Overview 26 Analog Input Subsystem 29 Input Modes 35 Input Ranges 37 Gain Settings 37 Channel List 38 Clocking 39 Triggering 41 ADC FIFO 42 Data format 43 Analog Output Subsystem 46 Single Update 46 Event bas...

Page 4: ...ty Software Support 95 Calibration 97 Calibration 98 Overview 98 When to calibrate 98 Appendix A Specifications 99 Appendix B Accessories 103 Accessories 104 Screw Terminal Panels 104 BNC Connection Panels 104 Thermocouple Input Racks 105 5B 7B OEM Distribution Panels 105 Mating cables connectors PCB connection board 105 Cables 106 19 Racks 106 Solid State Relay Backplane 106 Signal Conditioning E...

Page 5: ...Table of Contents iii Index 137 ...

Page 6: ...Q block diagram 26 Figure 8 PowerDAQ Multifunction Board front end 30 Figure 9 PowerDAQ Sample and Hold Board front end 31 Figure 10 PD2 MF Series Acquisition Process 32 Figure 11 PD2 MFS Acquisition Process 33 Figure 12 Single Ended Inputs 35 Figure 13 Differential Inputs 36 Figure 14 Digital Input Subsystem 49 Figure 15 PowerDAQ Software Structure 54 Figure 16 Communication between user applicat...

Page 7: ...ut Range Table 37 Table 11 Programmable Gains 37 Table 12 Channel List Format 38 Table 13 Programmable Gain Codes 38 Table 14 Different Clocking Combinations 40 Table 15 External Trigger Modes 42 Table 16 Data Format Table for a 16 bit Board 43 Table 17 PowerDAQ II 12 bit data format 43 Table 18 PowerDAQ II 14 bit data format 43 Table 19 PowerDAQ II 16 bit data format 43 Table 20 Bit Weight vs Inp...

Page 8: ...333 16L PD2 MF 16 400 14H PD2 MF 16 333 16H PD2 MF 64 400 14L PD2 MF 64 333 16L PD2 MF 64 400 14H PD2 MF 64 333 16H PD2 MF 16 1M 12L PD2 MF 16 500 16H PD2 MF 16 1M 12H PD2 MF 16 500 16L PD2 MF 64 1M 12L PD2 MF 64 500 16H PD2 MF 64 1M 12H PD2 MF 64 500 16L PowerDAQ PD2 MFS Multifunction Sample and Hold Series PD2 MFS 4 2M 14 PD2 MFS 8 2M 14 PD2 MFS 4 800 14 PD2 MFS 8 800 14 PD2 MFS 4 500 14 PD2 MFS...

Page 9: ... the various models available and lists what you need to get started Chapter 2 Installation and Configuration This chapter explains how to install and configure your PowerDAQ board Chapter 3 Architecture This chapter discusses the subsystems of your PowerDAQ board Chapter 4 PowerDAQ Software Development Kit This chapter describes the software for your PowerDAQ board Chapter 5 Calibration This chap...

Page 10: ...ghlight quick ways to get the job done or good ideas you might not discover on your own Note Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss or system crash Text formatted in bold typeface may also represent type that should be entered verbatim or a command as in the following example You can instruct users how to run setup usin...

Page 11: ...1 1 Introduction ...

Page 12: ... of the PowerDAQ board are 24 bit 66 MHz Motorola 56301 DSP Digital Signal Processor PCI Bus Host PC Interface PCI 2 1 Compliant Custom designed programmable gain amplifier Analog Input 16 64 channels 12 14 or 16 bit AD resolutions Analog Output 2 channels 1K DSP based FIFO Digital In 16 inputs Digital Out 16 inputs Three Counter Timers 8254 3 Clock In Gate control Auto calibration Extensive trigg...

Page 13: ... bit 16SE 8DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 64 2M 14H 2 2 MS s 14 bit 64SE 32DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 16 400 14L 400 kS s 14 bit 16SE 8DI A D Gains 1 10 100 1000 Two 12 bit D A PD2 MF 16 400 14H 400 kS s 14 bit 16SE 8DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 64 400 14L 400 kS s 14 bit 64SE 32DI A D Gains 1 10 100 1000 Two 12 bit D A PD2 MF 64 400 14H 400 kS s 14 bit 64...

Page 14: ...bit 16SE 8DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 64 333 16L 333 kS s 16 bit 64SE 32DI A D Gains 1 10 100 1000 Two 12 bit D A PD2 MF 64 333 16H 333 kS s 16 bit 64SE 32DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 16 500 16L 500 kS s 16 bit 16SE 8DI A D Gains 1 10 100 1000 Two 12 bit D A PD2 MF 16 500 16H 500 kS s 16 bit 16SE 8DI A D Gains 1 2 4 8 Two 12 bit D A PD2 MF 64 500 16L 500 kS s 16 bit 64...

Page 15: ...ld Two 12 bit D As PD2 MFS 4 1M 12 1 MS s 12 bit 4SE Simultaneous Sample Hold Two 12 bit D As PD2 MFS 8 1M 12 1 MS s 12 bit 8SE Simultaneous Sample Hold Two 12 bit D As PD2 MFS 4 300 16 300 kS s 16 bit 4SE Simultaneous Sample Hold Two 12 bit D As PD2 MFS 8 300 16 300 kS s 16 bit 8SE Simultaneous Sample Hold Two 12 bit D As PD2 MFS 4 500 16 500 kS s 16 bit 4SE Simultaneous Sample Hold Two 12 bit D ...

Page 16: ...8DI with Gains 1 2 5 10 Table 3 PD2 MFS Differential Upgrade Options PowerDAQ D A DIO and Counter Timer features All PowerDAQ boards have the following additional features Analog Output Two 12 bit 200 kHz DAC s Digital Input 16 TTL of which 8 can generate interrupts Digital Output 16 TTL Counter Timers Three 16 bit 8254 type PowerDAQ FIFO Upgrade options Any PowerDAQ multifunction board can have t...

Page 17: ...Chapter 1 Introduction 7 PD 32KFIFO Upgrade PowerDAQ II board from 1K FIFO to 32K FIFO PD 64KFIFO Upgrade PowerDAQ II board from 1K FIFO to 64K FIFO Table 4 FIFO upgrade options ...

Page 18: ......

Page 19: ...9 2 Installation and Configuration ...

Page 20: ...eater Windows 95 98 NT 4 0 2000 Workstation or Server Packing List In your PowerDAQ package you should have received A PowerDAQ board A user manual A CD containing the PowerDAQ software development kit SDK and documentation Note The CD label shows the version number of the SDK A calibration certificate Precautions PowerDAQ boards contain sensitive electronic components When handling your PowerDAQ ...

Page 21: ...on the back panel of your PC Save the screw 3 Insert the board into the PCI slot 4 Fasten the board s mounting bracket to your PC s back panel with the screw that held the slot cover 5 Inspect the board and ensure that it has been properly inserted in the slot 6 Replace the cover of your PC and turn on the power Note The PowerDAQ PCI interface must be set to 32 bit 5V power and signaling the defau...

Page 22: ...o and then the PowerDAQ welcome screen go to step 6 3 If the Setup program does not start automatically select Run from the Start menu 4 Enter D Setup exe in the Open textbox Substitute the correct letter if D is not the drive letter of your CD ROM drive 5 Click OK 6 As the Setup program runs you will be asked to enter information about your PowerDAQ configuration Unless you are an expert user and...

Page 23: ... 8 When the installation is complete you should restart your PC when prompted Confirming the Installation Once you have installed the PowerDAQ board and software on your PC you should confirm the installation Select Programs PowerDAQ Control Panel from the Start menu If the Control Panel applet is displayed and correctly identifies your PowerDAQ board the installation is correct Figure 1 Control P...

Page 24: ...o o t R O M L o w N o i s e D C D C P o w r D A Q Figure 2 Board connector layout Input Modes The analog input section multiplexes the active input channels 64 16 single ended or 32 8 differential to a single 12 or 16 bit successive approximation analog to digital converter ADC Single Ended PowerDAQ boards can be configured to operate with either a single ended or differential input Single ended i...

Page 25: ... using a 1 to 10 KΩ resistor Differential Inputs Differential inputs allow up to 32 channels Each differential channel uses two analog channels one analog channel connects to the positive input of the programmable gain amplifier and the other to the negative V1 Ain Ain RETURN AGND Figure 4 Differential Inputs V1 Ain Agnd ...

Page 26: ...aths reasonable being determined by the strength of the power signals and the amount of shielding Signal lines near devices that create high levels of electrical noise should be run through a metal cable trough above or below the work area Power lines poorly designed video monitors and switching power supplies solenoids electric arcs from breakers or welders and unshielded signal cables can affect...

Page 27: ...mpling speed Base address DMA Interrupt settings The PowerDAQ boards are configured automatically by the PCI bus on power up You do not have to set any base address DMA channels or interrupt levels Test Program After you have wired an application to your PowerDAQ board you should run the Simple Test program 1 Select Programs PowerDAQ Simple Test from the Start menu The Simple Test dialog box is di...

Page 28: ...red by Fujitsu PN FCN 245P096 G U Male http www fta fujitsu com 36 pin internal digital connector J2 Manufactured by Thomas and Betts PN 609 3627 Male http www thomasandbetts com 36 pin internal digital connector J4 Manufactured by Thomas and Betts PN 609 3627 Male http www thomasandbetts com 8 pin internal digital clock signal connector J6 Manufactured by Adam Tech PN PH2 08 TA SMT http www adam ...

Page 29: ...IN23 AIN21 AGND AIN18 AIN16 AIN6 AIN5 AIN3 AIN1 AGND DSP Trigger Input AO External Clock ADC Conversion Start Out Pacer clock out N C AGND ADC Channel List Start Input Burst Clock AIN62 AIN60 AIN59 AIN57 AIN47 AGND AIN44 AIN42 AIN40 AGND AIN29 AIN27 AIN25 AIN24 AIN14 AIN12 AGND AIN9 AGND AOUT0 AGND AOUT1 AGND AGND AIN54 AIN52 AIN50 AIN48 AIN39 AIN37 AIN35 AGND AIN32 AIN22 AIN20 AIN19 AIN17 AIN7 AG...

Page 30: ... Out Pacer clock out N C AGND ADC Channel List Start Input Burst Clock AIN54 Return AIN52 Return AIN51 Return AIN49 Return AIN39 Return AGND AIN36 Return AIN34 Return AIN32 Return AGND AIN21 Return AIN19 Return AIN17 Return AIN16 Return AIN6 Return AIN4 Return AGND AIN1 Return AGND AOUT0 AGND AOUT1 AGND AGND AIN54 AIN52 AIN50 AIN48 AIN39 AIN37 AIN35 AGND AIN32 AIN22 AIN20 AIN19 AIN17 AIN7 AGND AIN...

Page 31: ...2 33 34 35 36 CTR0 IN CTR0 OUT CTR0 GATE CTR1 IN CTR1 OUT DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 Burst Clock ADC Channel List Start Input Pacer Clock ADC Conversion Start Input DGND Burst Clock ADC Channel List Start Output CTR2 IN CTR2 OUT CTR2 GATE CTR1 GATE 5V 100 mA max DGND DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 DGND ADC Conversion Start Output Pacer Clock Output DGND Channel List D...

Page 32: ... lines 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 DGND DGND DGND DGND DGND DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DGND DGND DGND DGND DGND DGND DGND DGND DGND 5V 100 mA max DGND DOUT8 DOUT9 DOUT10 DOUT11 DOUT12 DOUT13 DOUT14 DOUT15 DGND DGND DGND DGND Table 8 Connector Pin Assignments for J4 ...

Page 33: ...onization Connector contains two pairs of clock signal lines The ADC Clock also known as the conversion clock The Channel List Clock also known as the scan clock or burst clock 1 2 3 4 5 6 7 8 CV_START_OUT CL_START_OUT CV_START_IN CL_START_IN DGND DGND DGND DGND Table 9 Connector Pin Assignment for J6 ...

Page 34: ......

Page 35: ...25 3 Architecture ...

Page 36: ...ain A m p 12 14 16 bit Sam pling A D Converter U pgradable 1k Sam ple A D C FIFO Channel Gain Control Logic Channel List FIFO A ln Pow er Conditioner 16 or 6 4 Channel A nalog M ultiplexer D igital O utput D river Conf iguration Calibration EEPRO M 32 Bit PCI Bus C o n t r o l A d d r e s s D a t a 16 I n t e r n a l D i g i t a l I O C o n n e c t o r s J 2 J 4 16 I n t e r b o a r d S y n c h r ...

Page 37: ... D FIFOs hold digitized samples until the DSP transfers them into the host memory via the PCI bus The default A D FIFO size is 1kS You can upgrade the A D FIFO size to 16kS or 32kS depending on your application Larger FIFOs give you smother operations especially at high acquisition rates and degrade response time in a case of control loop application The Calibration DACs provide voltages to adjust...

Page 38: ...l input lines 8 bit Schmidt trigger to catch logic level changes on digital input lines 16 bit output register to hold logical levels on digital output lines once data has been written Interrupt mechanism to notify DSP about interrupt conditions User Counter Timer subsystem includes Three 16 bit Intel 82C54 counter timers fully accessible Clock source selection and control logic Gate source select...

Page 39: ... of operation Fig 8 SE DF mode is selected for all input channels The output of the mux signal is fed into a instrumentation amplifier INA and then into a custom programmable gain amplifier PGA Channel numbers along with their gains are stored in the channel list This allows you to select different gains on a per channel basis Note Input muxes have high input impedance It is highly recommended to ...

Page 40: ... on the back side of the board Fig 9 SE or DF mode is selected by grounding negative input of the INA to the boards analog ground AGND Channel numbers along with their gains are stored in the channel list This allows you to select different gains on a per channel basis INA MUX A MUX B Analog input 0 Analog input N PGA SE DF switch control signal channel and gain control to range control calibratio...

Page 41: ...HAs between sampled and hold states When the SHA is in a sample state its output repeats its input In the hold state SHAs keep the output voltage at the same level at time of switching PGA INA SHA PGA INA SHA MUX SE DF switch control signal S H signal channel select signal to range control calibration circuitry and ADC Analog input 0 Analog input N Gain contro l signal ...

Page 42: ...re 32 Figure 10 PD2 MF Series Acquisition Process Time Channels Ch 0 Ch 1 Ch 2 Moment of digitizing Signal level at the moment of t0 t1 t2 Time Channels Ch 0 Ch 1 Ch 2 Moment of digitizing Signal level t0 t1 t2 Hold Sampl ...

Page 43: ...delay between acquisitions If the input signal frequency is relatively low 5 10 times lower then acquisition rate the difference in the acquired signal level is minimal Data acquisition is virtually simultaneous If the input signal has a fairly high frequency sequential acquisition can cause significant error in the digitized signal levels MFS board would be more suitable for such an application T...

Page 44: ...te Always use PowerDAQ MFS series of board if you require true difference between input channels levels and working with signals close to nyquist frequency Note Complete timing tables for all PowerDAQ boards are located Appendix A ...

Page 45: ...ts are shown diagrammatically in figure 12 See Table 5 for complete wiring instructions Note Unused channels should be shorted to ground using a 0 to 1KOhm resistor Figure 12 Single Ended Inputs Differential Inputs Differential inputs allow up to 32 channels Differential inputs use two analog input channels One channel connects to the positive input of the programmable gain amplifier and the other...

Page 46: ... and 8 form the high and low inputs of input channel 0 channels 1 and 9 that of input channel 1 Differential inputs are shown diagrammatically below See Table 6 for complete wiring instructions Note PowerDAQ MFS boards with DG option installed have the same number of differential and single ended channels V1 Ain Ain RETURN Agnd ...

Page 47: ... Table Gain Settings You can set a gain for each channel prior to acquisition Depending on your board there are three gain ranges MF PGL Gains MF PGH Gains MFS DG option Gains 1 10 100 1000 1 2 4 8 1 2 5 10 Table 11 Programmable Gains Note For low level signals you need high gains and you should use a PGL model For high level signals you need a low gain board and you should use the PGH model ...

Page 48: ...ach Channel List block written clears and overwrites the previous settings The Slow Bit is a special marker which guaranties longer settling time for a particular channel It is very useful when the signal is acquired has a high 100 or 1000 gain The Channel list has the following format Bit 8 Bits 7 and 6 Bits 5 to 0 Slow bit Gain Channel to acquire Table 12 Channel List Format Gain coding bits 7 6...

Page 49: ...ernal clock Continuous clocking or self retriggerable clock Additionally for internal or external clocks an active edge rising or falling can be selected Note The PowerDAQ board will generate an error condition each time a clock signal is applied before the board is ready to process it For example if you clock the board with a clock frequency higher than the rated aggregate rate the board reports ...

Page 50: ...ous Continuous Performs acquisition at maximum speed possible Less accurate than using the timebase Continuous or SW Internal MF boards only You can select the specific time between conversions Use this type of clocking when you want to increase settling time between acquisitions especially when your signal source has high output impedance Continuous External MF boards only Useful when one channel...

Page 51: ...ensitive You can select rising or falling edge to be active If the board is set up to start on an external trigger all clocks will be ignored until the pulse comes Acquisition continues until the stop trigger comes Note If CV Start clock is set to continuous or internal start stop the trigger is guaranteed to start and stop acquisition at the beginning of channel list If CV Start is external it s ...

Page 52: ...kS default up to 32kS depending on the FIFO option purchased When the PowerDAQ board acquires data in continuous mode data is written into the ADC FIFO When the FIFO becomes half full the DSP initiates data transfer from the ADC FIFO into the host memory When a minimal amount of data is to be transferred to the host memory in continuous acquisition mode it is 512 samples for 1kS FIFO 2048 samples ...

Page 53: ...es in any unused bit locations Table 16 Data Format Table for a 16 bit Board Table 17 PowerDAQ II 12 bit data format Table 18 PowerDAQ II 14 bit data format Table 19 PowerDAQ II 16 bit data format 1st channel 2nd channel last channel 1st channel sample sample sample sample bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 ...

Page 54: ...076295 Volts bit 0 10V unipolar 10V span 0 002442 Volts bit 0 000152590 Volts bit 5V bipolar 10V span 0 002442 Volts bit 0 000152590 Volts bit 10V bipolar 20V span 0 004884 Volts bit 0 000305180 Volts bit Table 20 Bit Weight vs Input Range 2 Determine the zero offset which depends on the input range selected 5V 10V unipolar 0 5V biploar 5V 10V biploar 10V Table 21 Displacement vs Input Range 3 Per...

Page 55: ...ffset from step 2 7 If a gain other than 1 was used for a selected channel divide the value received by the gain factor Doing this step last guarantees the maximal data accuracy 8 To convert voltage into analog output value you can use following formulas For 12 bit PowerDAQ board Value HexData AND 0xFFF XOR 0x800 BitWeight Displacement Gain For all other models Value HexData XOR 0x8000 BitWeight D...

Page 56: ...eform mode allows continuous waveform generation and is not limited by the amount of data The interrupt based data requests from the board will be received each time the DSP based FIFO is full with 2K samples on board FIFO you can load a maximum of 1024 samples at a time Note If the FIFO is empty or the last value is outputted the board continues outputting the last value Continuous polled I O Wav...

Page 57: ...MF S boards The channel list always contains channel 0 and 1 and are updated simultaneously Note The two channels are updated at the same time therefore you have to configure both DACs to the same mode of operation Data Format Table 22 Analog Output Data Format The analog outputs have a fixed output range of 10V Data representation is in straight binary To convert voltage into binary codes you can...

Page 58: ...se 11 MHz divisor 1 Every time a clock pulse comes the board reads the next value from the D A FIFO and converts it into a voltage and outputs the analog data on the selected channel Triggering The external trigger line can also be used as an analog output start and stop trigger You can select internal clock as the analog output timebase and use the trigger line to start and stop output Additional...

Page 59: ...em contains one 16 bit input register Digital inputs do not support clocked input it can only be used in software polled mode Eight lower lines of the digital input are connected to a latch register This register could be programmed to detect rising or and falling edges on those digital input lines Figure 14 Digital Input Subsystem 16 bit Input Register 8 bit Edge Detector and Latch Logic Input le...

Page 60: ...al input lines A 8 bit latch register has 1 bit per input line It is set to 1 when the configured edge is detected Additionally the logic fires an interrupt to the DSP to inform it when the configured conditions are met If you set up a latch configuration to watch for edges on several lines the interrupt fires as soon as any of the selected conditions happen However the interrupt will not be re fi...

Page 61: ...m one of the following four sources Software command 1 MHz internal timebase External clock input line UCT0 output line available for UCT1 and 2 Gate can be controlled from two sources Software command External gate input line Each of the UCT can be used in following modes Pulse generates one pulse with value frequency length Mode 1 Train generates pulse train with value frequency rate Pulse lengt...

Page 62: ...Chapter 3 Architecture 52 The UCT is extremely useful in combination with the external clock and trigger lines Using the UCT you can create very sophisticated acquisition setups ...

Page 63: ...53 4 PowerDAQ Software Development Kit PD SDK ...

Page 64: ... C Builder Examples Inprise C Builder 3 5 Delphi Examples for Inprise Delphi 3 4 Visual Basic Examples for MS Visual Basic VB3 Example for 16 bit VB3 VB5 Examples for V5 can use withVB6 VB6 Examples for VB6 Visual C Examples for MS Visual C 5 6 Include VB VC Delphi API declarations 16 bit VC files for 16 bit OS VB3 MS VB3 16 bit files with API Lib Library LIB files for VC Inprise Borland C Builder...

Page 65: ...00 operating system Location winNT system32 Files PwrDAQ32 dll 32 bit DLL PwrDAQ16 dll 16 bit DLL The DLLs have identical names for Windows 9x and Windows NT 2000 however they are implemented differently Both of them support the same API therefore PowerDAQ applications which do not use specific Win9x and WinNT 2000 functions would run on both OS PowerDAQ Libraries PowerDAQ SDK contains libraries f...

Page 66: ...C pwrdaq32 pas API function prototypes and structures file for Borland Delphi pwrdaq32 bas API function prototypes and structures file for Visual Basic pd_hcaps h boards capabilities definition file for C C pd_hcaps pas boards capabilities definition file for Borland Delphi pd_hcaps bas boards capabilities definition file for Visual Basic vbdll bas auxiliary functions to access PowerDAQ buffer fro...

Page 67: ...API function prototypes and structures file for 16 bit C C pwrdaq h driver constants and definitions file for 16 bit C C pdd_vb3 h auxiliary functions to access PowerDAQ structures from within VB v 3 0 pd_hcaps h boards capabilities definition file for 16 bit C C ...

Page 68: ...ompassed into the PowerDAQ dynamic link library DLL To inform application about hardware events the driver creates Win32 events Data is transferred from the board through the PCI bus and stored in the user level buffer The PowerDAQ API includes a set of information functions which allow user applications to get board specific information such as model serial number IRQ line etc PowerDAQ board PCI ...

Page 69: ...fore starting any operation and after completion release the subsystem close adapter and driver The manual explains generalized algorithms and important API calls For programming details see PowerDAQ Programming Guide API calls required for opening subsystems PdDriverOpen Opens driver _PdAdapterOpen Opens adapter only one process can open adapter at a time _PdAcquireSubsystem Acquire named subsyst...

Page 70: ...he input mode you need to OR your analog input configuration word with the input mode selection constants Input Mode Constant Single Ended 0 5V 0 Single Ended 0 10V AIB_INPRANGE Single Ended 5 5V AIB_INPTYPE Single Ended 10 10V AIB_INPTYPE AIB_INPRANGE Differential 0 5V AIB_INPMODE Differential 0 10V AIB_INPMODE AIB_INPRANGE Differential 5 5V AIB_INPMODE AIB_INPTYPE Differential 10 10V AIB_INPMODE...

Page 71: ...does not require buffering because the maximum number of samples acquired is less then the minimal size of the ADC FIFO Initialization Method A Reset the board PdAInReset Set up configuration _PdAInSetCfg Analog input configuration bits are defined in pdfw_def h file Recommended configuration for Method A is DwCfg AIB_CVSTART0 AIB_CVSTART1 for software clock DwCfg AIB_CVSTART0 AIB_CVSTART1 AIB_CLS...

Page 72: ...dAInSwClStart Note If you are using external pulses to clock the channel list start you have to address the situation when the next scan clock comes during your _PdAInGetSamples call This function will return the number of points that are stored in the buffer If the number of scans is equal to the board s A D FIFO size scan synchronization might be lost You need to be aware of these situations in ...

Page 73: ... bit in the channel list You might want to increase settling time for a particular channel with the high gain selected or a channel connected to a high output impedance signal See your board specifications to calculate how much slow bit affects time needed to acquire that channel ...

Page 74: ... the driver via Win32 events This means that you should program the board for asynchronous operation and use Win32 function such as WaitForSingleObject to wait until the driver notifies that data is acquired Initialization Reset the board _PdAInReset Allocate and register buffer with the board _PdAllocateBuffer Use as big a buffer as you need Buffer size is limited by the amount of memory installe...

Page 75: ...ove system performance PD 16KFIFO or PD 32KFIFO Initiate asynchronous operation _PdAsyncInit Use selected input configuration and events Provide dwAInClClkDiv to set up the desired scan rate Fill and pass channel list as it was explained in Method A Make sure that aggregate rate set up scan rate number of channels is lower or equal to the maximum board rate Set up event notification _PdAInSetPriva...

Page 76: ...while serving interrupts see note about interrupts On board A D FIFO overflows If error persists check interrupt settings and or purchase bigger A D FIFO option Reset events _PdSetUserEvents Call this function to notify the driver that events are processed Restart Stop asynchronous operation _PdAInAsyncStop _PdAInAsyncTerm This call stops asynchronous operation You need to call these functions bef...

Page 77: ...eBuffer Note External trigger If you want your acquisition process to be started or stopped by an external pulse connect your trigger source to the external trigger line and setup your analog input configuration word dwAInCfg with trigger settings as stated below ...

Page 78: ...a into the host memory only when the A D FIFO becomes half full For example if your board s FIFO size is 1kS acquisition rate is 100Hz and you put one channel into the channel list the board notifies the driver and application only after 5 seconds of acquisition no matter how small your frame is If you clock your board externally you will not get any response from the board until the board will ge...

Page 79: ... as you need The buffer size is limited by the amount of memory installed on your PC You can specify from two to N frames to use Frame size in scans notifies the driver when the application wants to receive eFrameDone events In the case of two frames per buffer we re dealing with the classic double buffering mechanism The larger number of frames makes the operations elastic and decreases probabili...

Page 80: ...quisition is stopped The reason could be a trigger pulse on external trigger line software command or buffer error Also if the application does not take data fast enough from the buffer and there is no room to place new incoming data Check other bits to find what caused acquisition to stop eBufferError data integrity was compromised because of lack of performance or system latency while serving in...

Page 81: ...ad This means that these frames can be reused for new data Reset events _PdSetUserEvents Call this function to tell the driver that events are processed Perform your application specific tasks At this point you can do whatever you want with the data Make sure that your procedure is short enough to process everything you need before the next eFrameDone event Otherwise the buffer can overflows and t...

Page 82: ...ffer overflow if the OS delays in responding The buffer should be big enough to accommodate from 0 33 to 1 second of streaming data Note Analog trigger pre and post triggers This is implemented in your user application or application yourself or using 3rd party software such as LabVIEW DASYLab DIADem TestPoint or HP VEE Analog trigger support has been implemented in these drivers Reading thermocou...

Page 83: ...led flag will be set To switch your buffer into this mode setup buffer as follows _PdRegisterBuffer Set dwWrapAround AIB_BUFFERRECYCLED to use recycled mode of the circular buffer This mode is explained in Appendix C One of the obvious reasons to use this mode is in situations when you cannot predict the exact time needed to process the data For example your control application monitors input data...

Page 84: ...available for more than 4 boards in one system It connects the CL and CV clock outputs from master board to CL and CV clock inputs of the slave boards To synchronize multi board acquisition you should program the master board CL or CV clock to use internal external or SW clocking and the slave boards to use external CL or CV clock Any of the Methods A thru D can be used The best way to set up mult...

Page 85: ...can create separate event objects for each subsystem using _PdAInSetPrivateEvent _PdAOutSetPrivateEvent _PdDInSetPrivateEvent _PdUctSetPrivateEvent When one or another subsystem needs an attention the appropriate event is set Subsystem thread wake up on WaitForSingleObject Win32 API calls and processes event as described above To release event objects use appropriate _PdxxxClearPrivateEvents Avera...

Page 86: ...Clock after the desired delay The PowerDAQ board is very flexible and can be configured in many different ways To convert analog input raw values to float voltages use the PdAInRawToVolts Note Shared interrupts and IRQ level PowerDAQ boards are designed to share interrupts We do not recommend PowerDAQ boards to share interrupts with devices like video and network cards or hard drives These devices...

Page 87: ...signed by the BIOS of your PC and if allowed it might be re assigned during the operation system boot up process If you have an Advanced Interrupt Controller on your motherboard just enable it in the BIOS this will allow you to use more than 16 generic interrupt lines If not use the manual settings to assign the interrupt to the PCI slot where PowerDAQ board is installed Modern motherboards can ea...

Page 88: ...ode using PCI interrupts Buffered polled I O waveform mode Auto retriggerable waveform mode Method A Polled I O update mode See SDK Examples SimpleAOut cpp SimpleTest vbp This method allows you to update analog output values immediately see Functional Overview for data format Initialization Reset the board _PdAInReset Output value Output analog output value _PdAOutPutValue ...

Page 89: ... for all subsystems Initialization Reset analog output _PdAOutReset Set analog output configuration _PdAOutSetCfg set dwConfig AOB_CVSTART0 to use 11 MHz internal base clock Set timebase _PdAOutSetCvClk use the same calculations to set up the timebase as it was described in the analog input subsystem Set up event object _PdAOutSetPrivateEvent Enable interrupt _PdAdapterEnableInterrupt Set events t...

Page 90: ...1 AOB_STOPTRIG0 AOB_STOPTRIG1 has the same functionality as for the analog input subsystem Wait for events and process them using WaitForSingleObject Win32 API call Event handler Check when event object was set _PdGetUserEvents Look at three events eFrameDone means that half of the D A FIFO is output eBufferDone eBufferError means that the entire buffer has been output and there is no more data av...

Page 91: ...PdAOutSwStopTrig Disable D A conversions _PdAOutEnableConv use 0 false as dwEnable De Initialize Disable interrupt if no other subsystem uses interrupt at that time _PdAdapterEnableInterrupt use dwEnable 0 Release event object _PdAOutClearPrivateEvent Clear subsystem and set both outputs to zero volt _PdAOutReset ...

Page 92: ...es for which it has buffer space the application must keep track of the number of the samples it writes Buffered polled I O waveform mode is easier to implement than event based and it is a good mode to use in single subsystem applications Initialization Reset analog output _PdAOutReset Set analog output configuration _PdAOutSetCfg set dwConfig AOB_CVSTART0 to use 11Mhz internal base clock Set tim...

Page 93: ...ocessor time to other processes Sleep n time for process to sleep depends on output rate Setup sleep time to about half the buffer output time Stop acquisition Issue stop trigger if external trigger was not configured _PdAOutSwStopTrig Disable D A conversions _PdAOutEnableConv use 0 false as dwEnable De Initialize Clear subsystem and set both outputs to zero volt _PdAOutReset ...

Page 94: ...nd of the buffer Use this mode when you need a continuous waveform shorter or equal to the D A FIFO size The benefit of this mode is that it does not use any CPU time everything is run using the PowerDAQ on board DSP Initialization Reset analog output _PdAOutReset Set analog output configuration _PdAOutSetCfg set dwConfig AOB_CVSTART0 AOB_DACBLK0 AOB_DACBLK1 AOB_REGENERATE to use 11 MHz internal b...

Page 95: ...nv use 1 as dwEnable _PdAOutSwStartTrig Stop acquisition Reset analog output subsystem _PDAOutReset Note Board will stop waveform generation when it reaches the end of the buffer To convert float voltages to raw values use function PdAOutVoltsToRaw TIP ...

Page 96: ...event when it detects a specified edge on the selected input line The eight lower lines are edge sensitive Method A Polled I O See SDK Example SimpleTest dpr Initialization Reset digital subsystem _PdDOutReset sets output lines to logical zero _PdDInReset clears latch and configuration register Input Output Read digital inputs _PdDInRead Write digital outputs _PdDOutWrite Set up digital input conf...

Page 97: ... latch contains 1 in the appropriate bit Clear status of digital input latch _PdDInClearData clears latch register and re enables edge detection on the line which previously caused an event Acquiring digital signals as analog In an application where you need to acquire some digital signals along with analog input you can build a simple D A converter Using a resistor ladder creates a simple D A con...

Page 98: ...ler Initialization Reset digital input subsystem _PdDInReset clears latch and configuration register Set up digital input configuration Set up edge sensivity configuration _PdDInSetCfg use this function to specify input line and an edge to be detected Configuration word is explained in Digital I O Architecture section of this manual _PdAdapterEnableInterrupt with dwEnable 1 _PdDInSetPrivateEvent s...

Page 99: ...iously caused an event Re enable events _PdSetUserEvent use DigitalIn as a subsystem name There is only one digital input event defined eDInEvent It means that one or more edges were detected De Initialization Disable interrupts if there is no other subsystem running _PdAdapterEnableInterrupt with dwEnable 0 Release event object and clear user level events _PdDInClearPrivateEvent release the event...

Page 100: ...to be built Additionally counter timers can generate events when they reach zero count These events can be used to clock other subsystems and perform various operations Programming of Intel 82C54 can be difficult because of it has various modes and settings To make it easy to you we provided definitions needed and a set of example functions in uct_progr c file located in the same folder with UCTEv...

Page 101: ...unter timer eUct0Event eUct1Event and eUct2Event Event handler Check event _PdGetUserEvent could return eUct0Event eUct1Event or eUct2Event flags in the status word Read status of UCT output _PdUctGetStatus function returns current state of the UCT output Re enable events _PdSetUserEvent De Initialization Disable interrupts if there is no other subsystem running _PdAdapterEnableInterrupt with dwEn...

Page 102: ...Chapter 4 PowerDAQ Software SDK 92 Note To write to the counter timer an input clock must be applied to appropriate UCT You can control the gate using the API call _PdUctSwSetGate ...

Page 103: ...tmeter application displaying up to 64 channels Stream4 exe continuous acquisition and stream to disk application Visual BASIC examples Versions supported VB 3 16 bit VB 5 and 6 32 bit Examples supplied SimpleTest application which allows Analog Input Analog Output Digital Input Digital Output and Counter Timer operation This program also allows simultaneous subsystem operation Additional examples...

Page 104: ...er operation This program also allows simultaneous subsystem operation Borland C Builder examples Versions supported Inprise Borland 3 5 Examples supplied Stream4 exe continuous acquisition and stream to disk application Note The include files for the above languages may have the same file name This means they can be used with either language ...

Page 105: ... installing the PowerDAQ software you must re install the PowerDAQ software to include support for this new third party package The following third party software is supported Software Version Supports multiple PowerDAQ Boards What s included LabVIEW 5 x or greater YES Extensive VI s including click and replace Vis HP VEE 5 x or greater YES Examples DASYLab 4 x or greater NO Examples Test Point 3 ...

Page 106: ......

Page 107: ...97 5 Calibration ...

Page 108: ...ccuracy better than 0 005 resolution 100 uV or better Any type of PowerDAQ screw terminal PD CAL Program The PowerDAQ calibration software is included with the CD The PD_Cal program allows you to recalibrate the board All boards shipped are fully calibrated and do not require additional calibration The PD CAL program is located in the PowerDAQ Applications directory or can be accessed by selecting...

Page 109: ...99 A Appendix A Specifications ...

Page 110: ...Appendix A Specifications 100 ...

Page 111: ...450 0 ns 3 0 us 8 PD2 MF 50 16L 16 50 kHz High 20 0 us 80 0 us 9 PD2 MF 50 16H 16 50 kHz Low 20 0 us 50 0 us A PD2 MF 100 16L 16 100 kHz Low 10 0 us 50 0 us B PD2 MF 100 16H 16 100 kHz High 10 0 us 50 0 us C PD2 MF 333 16L 16 333 kHz High 3 0 us 20 0 us D PD2 MF 333 16H 16 333 kHz Low 3 0 us 10 0 us E PD2 MF 500 16L 16 500 kHz High 2 0 us 20 0 us F PD2 MF 500 16H 16 500 kHz Low 2 0 us 10 0 us PD2 ...

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Page 113: ...103 B Appendix B Accessories ...

Page 114: ...it Includes PD STP 9616 PD CBL 96 and PD CBL 37 for 4 8 16 channel boards PD STP 3716 Low cost Screw Terminal Panel with 37 pin connector for 16 channel boards PD STP 3716 KIT Complete Kit Includes PD STP 3716 PD CBL 9637 for 16 channel boards BNC Connection Panels PD BNC 16 16 channel BNC panel for 16 channel boards PD BNC 16 KIT Complete Kit Includes PD BNC 16 PD CBL 96 PD CBL 37 for 16 channel ...

Page 115: ...ts 16 or 64 channel PowerDAQ II board to two 50 way IDC headers Mating cables connectors PCB connection board PD CONN Mating connector with metal cover Includes Fujitsu PN FCN 230C096 C E and FCN 247J096 G E PD CONN CBL 96 way pinless 0 5m round shielded cable with metal cover plate bare wires at one end PD CONN PCB PowerDAQ mating connector with PCB attached PD CONN STR Individual Fujitsu connect...

Page 116: ...mounting bracket PD CBL 37TP DIO Twisted pair cable set 37 way 1m D sub cable Internal cable with mounting bracket PD CBL 5B 18 ribbon cables that connect from the PD 5BCONN to 5B xx racks PD CBL 7B 18 ribbon cables that connect from the PD 7BCONN to 7B xx racks PD CBL 9626 18 round shielded cable that connects from the PD 5BCONN to PD STP 16 or PD BNC 16 PD CBL SYNC4 Internal cable to synchronize...

Page 117: ... and 8 programmable gain amplifies not combined PD SCXU FG16 16 Anti aliasing filters combined with 16 programmable gain amplifiers PD SCXU TJ8 8 J type isolated thermocouple PD SCXU TJ16 16 J type isolated thermocouple PD SCXU TK8 8 K type isolated thermocouple PD SCXU TK16 16 K type isolated thermocouple PD SCXU S8 8 channel isolated strain gauge PD SCXU S16 16 channel isolated strain gauge PD S...

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Page 119: ...109 C Appendix C Application Notes ...

Page 120: ...tion of the OS and active applications to reside in memory This is to prevent code and or data from frequently being swapped to disk Consequently if continuous gap free acquisition is to be performed the buffer should be large enough to hold all acquired data for the maximum time period expected between application execution latency and the time required for the application to process all data in ...

Page 121: ...ircular Buffer Recycled Circular Buffer In all three modes data is written to the beginning of the buffer at the start of acquisition The three modes differ in what is done when the end of the buffer is reached and if the buffer head catches up with the buffer tail Single Buffer In the Single Buffer mode acquisition stops when the buffer end is reached In this mode the application can access the b...

Page 122: ... application The data acquisition operation continues until the application issues a stop command to the driver If the application cannot keep up with the acquisition process and the buffer overflows then acquisition is stopped and the error condition is reported Recycled Circular Buffer The Recycled Circular Buffer mode is similar to the Circular Buffer mode with the exception in that when the he...

Page 123: ... the much simpler single and double buffer mechanisms in essence it is actually a superset of the simpler buffers The ACB configured in the single buffer mode will behave just as the simple ordinary single buffer If the ACB is configured as Circular Buffer with two frames it will behave as a double buffer With multiple frames the ACB can be used in algorithms that were designed for buffer queues T...

Page 124: ...d a low pass filter resistors should be installed into the R0A and R8A positions and a capacitor into the C0B position for the channel 0 and channel 8 pair and similarly for the other pairs Note that as supplied by the factory the RxA resistors have zero Ohm jumpers installed High pass filter In order to build a high pass filter capacitors should be installed into the R0A and R8A positions and a r...

Page 125: ...115 D Appendix D Warranty ...

Page 126: ...PARTMENT OF UNITED ELECTRONIC INDUSTRIES CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can reasonably be expected to result in a significant injury to the user or c...

Page 127: ...misuses accident negligence failure or electrical power or modification by the Customer without United Electronics Industries approval Final determination of warranty eligibility shall be made by United Electronics Industries If a warranty claim is considered invalid for any reason the Customer will be charged for services performed and expenses incurred by United Electronics Industries in handlin...

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Page 129: ...119 E Appendix E Glossary ...

Page 130: ...causes the stepping in the Channel List ADC Channel List Start Signal used to start the A D acquisition of channels in the channel list The triggering edge of this signal falling edge enables the ADC Conversion Start signals Alias A false lower frequency component that appears in sampled data acquired at too low a sampling rate Analog Trigger A trigger that occurs at a user selected point on an in...

Page 131: ...5 V to 5 V Bit One binary digit either 0 or 1 Block Mode A high speed data transfer in which the address of the data is sent followed by a specified number of back to back data words Burst Mode A high speed data transfer in which the address of the data is sent followed by back to back data words while a physical signal is asserted Bus The group of conductors that interconnect individual circuitry...

Page 132: ...ters containing control bits to initiate control signals to various onboard subsystems CMRR Common Mode Rejection Ratio A measure of an instrument s ability to reject interference from a common mode signal usually expressed in decibels dB Code Generator A software program controlled from an intuitive user interface that creates syntactically correct high level source code in languages such as C or...

Page 133: ...lock pulses timing such as the Intel 8254 device Coupling The manner in which a signal is connected from one location to another Crosstalk An unwanted signal on one channel due to an input on a different channel Current Drive Capability The amount of current a digital or analog output channel is capable of sourcing or sinking while still operating within voltage range specifications Current Sinkin...

Page 134: ...d possibly generating control signals with D A and or DIO boards in the same PC Data point Digitized data from one or more channels taken at the same or virtually same time dB Decibel The unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts Differential Input An analog input consisting of two terminals both of which are isolated from com...

Page 135: ...can be sequentially accessed by more than one controller or processor but not simultaneously accessed Also known as shared memory Dual Ported Memory Memory that can be simultaneously accessed by more than one controller or processor Dynamic Range The ratio of the largest signal level a circuit can handle to the smallest signal level it can handle usually taken to be the noise level normally expres...

Page 136: ...he first data stored is the first data sent to the acceptor Fixed Point A format for processing or storing numbers as digital integers Floating Point A format for processing or storing numbers in scientific exponential notation digits multiplied by a power of 10 Function A set of software instructions executed by a single line of code that may have input and or output parameters and returns a valu...

Page 137: ...istortion products to the overall rms signal level The test signal is two sine waves added together according to the following standards INL Integral Non linearity A measure in LSB of the worst case deviation from the ideal A D or D A transfer characteristic of the analog I O circuitry Input Bias Current The current that flows into the inputs of a circuit Input Impedance The measured resistance an...

Page 138: ...e transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces IPC Interprocess Communication Protocol by which processes can pass messages Messages can be either blocks of data and information packets or instructions and requests for pro cess es to perform actions A process can send messages to itself other ...

Page 139: ...hertz 2 mega the prefix for 1 048 576 or 220 when used with B to quantify data or computer memory Mbytes s A unit for data transfer that means 1 million or 106 bytes s MMI Man Machine Interface also Human Machine Interface The means by which an operator interacts with an industrial automation system often a GUI Multitasking A property of an operating system in which several processes can be run si...

Page 140: ... OLE is object enabling system software Through OLE Automation an application can dynamically identify and use the services of other applications to build powerful solutions using packaged software OLE also makes it possible to create compound documents consisting of multiple sources of information from different applications OLE Controls See ActiveX Controls Operating System Base level software t...

Page 141: ...riginally developed by Intel to replace ISA and EISA It is achieving widespread acceptance as a standard for PCs and work stations it offers a theoretical maximum transfer rate of 132 Mbytes s PID Control A three term control mechanism combining proportional integral and derivative control actions Also see proportional control integral control and derivative control Pipeline A high performance pro...

Page 142: ...adjusted used for manual adjustment of electrical circuits and as a transducer for linear or rotary position Pretriggering The technique used on a DAQ board to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition Programmed I O The standard method a CPU uses to access an I O device each byte of data i...

Page 143: ...rors It does not include offset and gain errors of the circuitry feeding the ADC Resolution The smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 percent of full scale Resource Locking A technique whereby a device is ...

Page 144: ...ires and stores an analog voltage on a capacitor for a short period of time SNR Signal to Noise Ratio The ratio of the overall rms signal level to the rms noise level expressed in dB Software Trigger A programmed event that triggers an event such as data acquisition SPDT Single Pole Double Throw A property of a switch in which one terminal can be connected to one of two other terminals SSH Simulta...

Page 145: ...nputs are grounded T TCP IP A set of standard protocols for communicating across a single network or interconnected set of networks The Internet Protocol IP for the low level service of taking data and packaging of components and Transmission Control Protocol TCP for high reliability data transmissions THD Total Harmonic Distortion The ratio of the total rms signal due to harmonic distortion to th...

Page 146: ...nding electrical signal Transfer Rate The rate measured in bytes s at which data is moved from source to destination after software initialization and set up operations the maximum rate at which the hardware can operate U Unipolar A signal range that is always positive for example 0 to 10 V Z Zero Overhead Looping The ability of a high performance processor to repeat instructions without requiring...

Page 147: ...nit 63 _PdClearPrivateEvent 73 _PdDInClearData 85 _PdDInGetStatus 85 _PdDInRead 84 _PdDInReset 84 _PdDInSetCfg 84 _PdDInSetPrivateEvent 73 _PdDOutReset 84 _PdDOutWrite 84 _PdFReeBuffer 65 _PdGetUserEvents 64 _PdImmediateUpdate 70 _PdRegisterBuffer 62 _PdSetPrivateEvent 73 _PdUctReset 89 _PdUctSerCfg 89 _PdUctSetPrivateEvent 89 _PdUctSetPrivateEvent 73 _PdUnregisterBuffer 65 8 82C54 27 A A D FIFO 2...

Page 148: ...s 14 Digital I O subsystem 84 Digital I O subsystem 27 47 DMA 16 E eBufferDone 64 eBufferError 64 Edge detection for DIO 86 eFrameDone 64 eStopped 64 Event based waveform 44 F FIFO Upgrades 6 Frame size 69 Fujitsu Connector 17 Functional Overview 25 G Gain settings 36 Gate source 27 Glossary 120 H high pass filter 114 HP VEE Support 93 I Include files 54 Input impedance 28 Input Modes 13 Input mux...

Page 149: ...84 Pre Post triggers 69 Programmable Gain Amplifier26 Programming subsystems 57 pwrdaq bas 54 pwrdaq h 54 pwrdaq pas 54 Pwrdaq sys 53 pwrdaq16 bas 55 PwrDAQ16 dll 53 pwrdaq16 h 55 PwrDAQ32 dll 53 pwrdaq32 h 54 pwrdaq32 hpp 54 pwrdaq32 pas 54 Pwrdaq95 vxd 52 R Recycled mode acquisition 71 S Sample and Hold Amplifiers 29 SDK structure 52 Simple Test 16 Single Ended 13 34 Single scan operation 59 Sin...

Page 150: ...Index 140 voltage divider 114 W WaitForSingleObject 64 WaitForSingleObject 73 Warranty 116 Waveform auto retriggerable 82 Waveform buffered event based 77 Waveform buffered polled I O 80 Windows 9x 53 ...

Page 151: ... Can you find information easily Yes No Were you able to install the PowerDAQ boards Yes No Were you able to connect the PowerDAQ board to the accessories Yes No Did you find any technical errors Yes No Is the manual size appropriate Yes No Are the design type style and layout attractive Yes No Is the quality of illustrations satisfactory Yes No How would you rate this manual Excellent Good Fair P...

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