United Electronic Industries PD2-MF, User Manual

Page: 37 / 152

Chapter 3: Architecture
27
Analog Input subsystem includes:
•
The Input multiplexor (MUX) selects which channels to
acquire. The channel list (CL) FIFO controls the input
muxes. PD2-MFS boards have sample-and-hold amplifiers
(SHA) preceding the muxes. SHA amplifiers sample all
input channels simultaneously and then hold the acquired
voltages while the ADC converts channel by channel.
•
The Programmable Gain Amplifier (PGA) amplifies an
input signal in order to provide adequate voltage to the
analog-to-digital converter (ADC). The PGA amplification
depends on the board model and can be software
selected {1,2,4,8} or {1,10,100,1000} for MF series boards
and {1,2,5,10} for MFS boards when the differential gain
(DG) option is installed. Gains are software selectable on
a per-channel basis.
•
The A/D FIFOs hold digitized samples until the DSP
transfers them into the host memory, via the PCI bus. The
default A/D FIFO size is 1kS. You can upgrade the A/D
FIFO size to 16kS or 32kS depending on your application.
Larger FIFOs give you smother operations especially at
high acquisition rates and degrade response time in a
case of control loop application.
•
The Calibration DACs provide voltages to adjust the
offset and gain settings. All boards are factory calibrated
for each input range and mode specified.
•
The Timing, triggering and clocking controls allow you to
select the timebase, clock and triggering sources, “slow
bit” and other options.
•
The Interrupt mechanism notifies the DSP about interrupt
conditions
Analog Output subsystem includes:
•
DSP based D/A FIFO keeps up to 2kS of digitized
waveform values.
•
Digital-to-analog converter (DAC) converts digitized
waveform values into analog output voltages.
•
Calibration DACs provide voltages to adjust offset and
gain of analog output.