Ublox NINA-B50 Series, Hardware Integration Manual

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NINA-B50 series - Hardware integration manual
UBX-22021116 - R02 Module integration Page 15 of 57
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2.3.2 Approved antenna designs
NINA-B50 series modules come with a pre-certified design that can significantly reduce costs and
save time during the certification process. To leverage this benefit, customers must implement an
antenna layout that fully complies with the u-blox reference design outlined in Figure 9 and Figure
10. Reference design source files are available from u-blox on request. 1
Designers integrating a u-blox reference design into an end-product assumes sole responsibility for
any unintentional emission levels produced by the end product.
For Bluetooth operation, NINA-B50 series modules have been tested and approved for use with the
antennas listed in the
Pre-approved antennas list .
⚠
To ensure that the compliance and pre-certification of u-blox modules with the various regulatory
bodies remains valid, use only the external antennas listed in the
Pre-approved antennas list .
Reference design source files are available from u-blox on request.
⚠
If the module is integrated with other antennas, the OEM installer must certify the design with
respective regulatory agencies.
2.4 Data interfaces
2.4.1 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
NINA-B50 series modules support two LPUART interfaces, LPUART0 and LPUART1 , for data
communication and firmware upgrade. The LPUART can continue operating while the processor is in
low-power mode if an appropriate peripheral clock is available.
Each UART supports the following signals:
• Data lines ( RXD as input, TXD as output)
• Hardware flow control lines ( CTS as input, RTS as output)
Both the UARTs can be used in 4-wire mode with hardware flow control, or in 2-wire mode with TXD
and RXD only.
☞
2-wire mode is not recommended as it is prone to buffer overruns.
The UART interface is also used for firmware upgrade. See also Open CPU software .
It is advisable to connect LPUART0 to a header for firmware upgrade or make the interface signals
accessible as test points.
The IO level of the UARTs follows VCC_IO .
2.4.2 Low Power Serial peripheral interface (LPSPI)
NINA-B50 supports two Low-power Serial Peripheral Interface (LPSPI) interfaces, LPSPI0 and
LPSPI1 .
Main and Sub node operations are possible on both interfaces. When configured in MAIN mode, both
the interfaces support up to 4 peripheral chip selects each.
1 Reference design files to be made available only after certification