TQ MBa57 Series, User Manual, Page: 14 / 62

User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH Page 9
4.1.1.3 Pinout TQMa57xx (continued)
Table 5: Pinout connector X2, (TQMa57xx: X2)
Ball Type Level Group Signal Pin Signal Group Level Type Ball
– P 5 V Power VDD5V 1 2 VDD5V Power 5 V P –
– P 5 V Power VDD5V 3 4 VDD5V Power 5 V P –
– P 5 V Power VDD5V 5 6 VDD5V Power 5 V P –
– P 5 V Power VDD5V 7 8 VDD5V Power 5 V P –
– P 0 V GND DGND 9 10 VDD5V Power 5 V P –
– P 0 V GND DGND 11 12 DGND GND 0 V P –
– P 3.3 V BAT V_BAT 13 14 DGND GND 0 V P –
– P 0 V GND DGND 15 16 DGND GND 0 V P –
F6 I/O 3.3 V ENET
PR1_MDIO_DATA /
GMAC_MDIO_DATA
17 18 WAKEUP0 Config 3.3 V I AD17
D3 O 3.3 V ENET
PR1_MDIO_MDCLK /
GMAC_MDIO_MCLK
19 20 GPIO3_29_G2 GPIO 3.3 V I/O G2
– P 0 V GND DGND 21 22 PR1_MII1_TXEN ENET 3.3 V O E4
A4 I 3.3 V ENET
PR1_MII1_CRS /
RGMII1_RXD0
23 24 PR1_MII1_MT_CLK ENET 3.3 V I C1
B5 I 3.3 V ENET
PR1_MII1_COL /
RGMII1_RXD1
25 26 DGND GND 0 V P –
B4 I 3.3 V ENET
PR1_MII1_RXLINK /
RGMII1_RXD2
27 28
PR1_MII1_TXD1 /
RGMII1_TXC
ENET 3.3 V O D5
B3 I 3.3 V ENET
PR1_MII1_RXER /
RGMII1_RXD3
29 30
PR1_MII1_TXD0 /
RGMII1_TXCTL
ENET 3.3 V O C2
– P 0 V GND DGND 31 32 PR1_MII1_TXD2 ENET 3.3 V O E6
D6 I/O 3.3 V ENET
PR1_MII1_RXD2 /
RGMII1_TXD0
33 34 PR1_MII1_TXD3 ENET 3.3 V O F5
B2 I/O 3.3 V ENET
PR1_MII1_RXD3 /
RGMII1_TXD1
35 36
PR1_MII1_RXD0 /
RGMII1_RXCTL
ENET 3.3 V I A3
C4 I/O 3.3 V ENET
PR1_MII1_RXDV /
RGMII1_TXD2
37 38
PR1_MII1_RXD1 /
RGMII1_RXC
ENET 3.3 V I C5
C3 I/O 3.3 V ENET
PR1_MII1_MR_CLK /
RGMII1_TXD3
39 40 DGND GND 0 V P –
– I 5 V USB VUSB_VBUS2 41 42 GPIO3_30_H7 GPIO 3.3 V I/O H7
– I 5 V Config PMIC_PWRON# 43 44 PR2_MDIO_DATA ENET 3.3 V I/O D14
K14 I 1.8 V Config E–FUSE_1V8 45 46 PR2_MDIO_MDCLK ENET 3.3 V O C14
– P 0 V GND DGND 47 48 DGND GND 0 V P –
A13 I 3.3 V ENET PR2_MII0_MR_CLK 49 50 PR2_MII0_MT_CLK ENET 3.3 V I F12
G12 I 3.3 V ENET PR2_MII0_RXER 51 52 PR2_MII0_TXEN ENET 3.3 V O B12
C15 I 3.3 V ENET PR2_MII0_RXD[0] 53 54 PR2_MII0_TXD[0] ENET 3.3 V O E14
A18 I 3.3 V ENET PR2_MII0_RXD[1] 55 56 DGND GND 0 V P –
A19 I 3.3 V ENET PR2_MII0_RXD[2] 57 58 PR2_MII0_TXD[1] ENET 3.3 V O A12
F14 I 3.3 V ENET PR2_MII0_RXD[3] 59 60 PR2_MII0_TXD[2] ENET 3.3 V O B13
– P 0 V GND DGND 61 62 PR2_MII0_TXD[3] ENET 3.3 V O A11
G14 I 3.3 V ENET PR2_MII0_RXDV 63 64 PR2_MII0_COL ENET 3.3 V I F15
A16 I 3.3 V ENET PR2_MII0_RXLINK 65 66 PR2_MII0_CRS ENET 3.3 V I B18
F21 I/O 3.3 V GPIO GPIO6_16_F21 67 68 DGND GND 0 V P –
B26 I/O 3.3 V GPIO GPIO6_19_B26 69 70 PR2_MII1_RXLINK ENET 3.3 V I C17
B25 I/O 3.3 V SPI SPI1_D0 71 72 PR2_MII1_CRS ENET 3.3 V I E17
F16 I/O 3.3 V SPI SPI1_D1 73 74 PR2_MII1_COL ENET 3.3 V I D18
– P 0 V GND DGND 75 76 GPIO3_1_AF9 GPIO 3.3 V I/O AF9
A25 O 3.3 V SPI SPI1_SCLK 77 78 NMIN_DSP Config 3.3 V I D21
A24 O 3.3 V SPI SPI1_CS0 79 80 DGND GND 0 V P –