TQ MBa57 Series, User Manual

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User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH Page 33
4.2.11 PCIe (continued)
Table 40: Pinout PCIe, X41
Pin Signal Remark
A1 NC –
A2 VCC12V_PCIE See Table 39
A3 VCC12V_PCIE See Table 39
A4 DGND –
A5 NC –
A6 NC –
A7 NC –
A8 NC –
A9 VCC3V3_PCIE See Table 39
A10 VCC3V3_PCIE See Table 39
A11 PERST# Connected to STKRST#. Connection to PCIE_RST# (from I
2
C port expander) as assembly option.
A12 DGND –
A13 MPCIE_SLOT_CLKP PCIE clock from clock generator
A14 MPCIE_SLOT_CLKN PCIE clock from clock generator
A15 DGND –
A16 PCIE_RXP0 100 nF in series
A17 PCIE_RXN0 100 nF in series
A18 DGND –
A19 NC –
A20 DGND –
A21 NC –
A22 NC –
A23 DGND –
A24 DGND –
A25 NC –
A26 NC –
A27 DGND –
A28 DGND –
A29 NC –
A30 NC –
A31 DGND –
A32 NC –
B1 VCC12V_PCIE See Table 39
B2 VCC12V_PCIE See Table 39
B3 VCC12V_PCIE See Table 39
B4 DGND –
B5 I2C4_SCL –
B6 I2C4_SDA –
B7 DGND –
B8 VCC3V3_PCIE See Table 39
B9 NC –
B10 VCC3V3_PCIE See Table 39
B11 PCIE_WAKE# Assembly option: 10 kΩ PU to 3.3 V or GND. Default: none.
B12 NC –
B13 DGND –
B14 PCIE_TXP0 100 nF in series on TQMa57xx
B15 PCIE_TXN0 100 nF in series on TQMa57xx
B16 DGND –
B17 NC –
B18 DGND –
B19 NC –
B20 NC –
B21 DGND –
B22 DGND –
B23 NC –
B24 NC –
B25 DGND –
B26 DGND –
B27 NC –
B28 NC –
B29 DGND –
B30 NC –
B31 NC –
B32 DGND –