User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 10
Pinout TQMa57xx (continued)
Table 6:
Pinout connector X3, (TQMa57xx: X3)
Ball
Type
Level
Group
Signal
Pin
Signal
Group
Level
Type
Ball
N6
O
1.8 V
GPMC
GPMC_BE#[0] (GPIO2_26)
1
2
DGND
GND
0 V
P
–
M4
O
1.8 V
GPMC
GPMC_BE#[1] (GPIO2_27)
3
4
GPMC_CLK (GPIO2_22)
GPMC
1.8 V
O
P7
M6
I/O
1.8 V
Boot/GPMC
GPMC_AD[0] (GPIO1_6)
5
6
GPMC_CS0 (GPIO2_19)
GPMC
1.8 V
O
T1
M2
I/O
1.8 V
Boot/GPMC
GPMC_AD[1] (GPIO1_7)
7
8
GPMC_OE#_RE# (GPIO2_24)
GPMC
1.8 V
O
M5
–
P
0 V
GND
DGND
9
10
GPMC_WE# (GPIO2_25)
GPMC
1.8 V
O
M3
L5
I/O
1.8 V
Boot/GPMC
GPMC_AD[2] (GPIO1_8)
11
12
GPMC_ADV#_ALE
(GPIO2_23)
GPMC
1.8 V
O
N1
M1
I/O
1.8 V
Boot/GPMC
GPMC_AD[3] (GPIO1_9)
13
14
GPMC_A[1] (GPIO7_4)
GPMC
1.8 V
O
T9
L6
I/O
1.8 V
Boot/GPMC
GPMC_AD[4] (GPIO1_10)
15
16
GPMC_A[2] (GPIO7_5)
GPMC
1.8 V
O
T6
L4
I/O
1.8 V
Boot/GPMC
GPMC_AD[5] (GPIO1_11)
17
18
DGND
GND
0 V
P
–
L3
I/O
1.8 V
Boot/GPMC
GPMC_AD[6] (GPIO1_12)
19
20
GPMC_A[3] (GPIO7_6)
GPMC
1.8 V
O
T7
L2
I/O
1.8 V
Boot/GPMC
GPMC_AD[7] (GPIO1_13)
21
22
GPMC_A[4] (GPIO1_26)
GPMC
1.8 V
O
P6
L1
I/O
1.8 V
Boot/GPMC
GPMC_AD[8] (GPIO7_18)
23
24
GPMC_A[5] (GPIO1_27)
GPMC
1.8 V
O
R9
–
P
0 V
GND
DGND
25
26
GPMC_A[6] (GPIO1_28)
GPMC
1.8 V
O
R5
K2
I/O
1.8 V
Boot/GPMC
GPMC_AD[9] (GPIO7_19)
27
28
GPMC_A[7] (GPIO1_29)
GPMC
1.8 V
O
P5
J1
I/O
1.8 V
Boot/GPMC
GPMC_AD[10] (GPIO7_28)
29
30
GPMC_A[8] (GPIO1_30)
GPMC
1.8 V
O
N7
J2
I/O
1.8 V
Boot/GPMC
GPMC_AD[11] (GPIO7_29)
31
32
GPMC_A[9] (GPIO1_31)
GPMC
1.8 V
O
R4
H1
I/O
1.8 V
Boot/GPMC
GPMC_AD[12] (GPIO1_18)
33
34
DGND
GND
0 V
P
–
J3
I/O
1.8 V
Boot/GPMC
GPMC_AD[13] (GPIO1_19)
35
36
GPMC_A[10] (GPIO2_0)
GPMC
1.8 V
O
N9
H2
I/O
1.8 V
Boot/GPMC
GPMC_AD[14] (GPIO1_20)
37
38
GPMC_A27_AF4 (GPIO3_19)
GPMC
3.3 V
O
AF4
H3
I/O
1.8 V
Boot/GPMC
GPMC_AD[15] (GPIO1_21)
39
40
GPMC_A27_G1 (GPIO3_31)
GPMC
3.3 V
O
G1
AD9
I/O
3.3 V
GPIO
GPIO3_0_AD9
41
42
DGND
GND
0 V
P
–
B19
I
3.3 V
ENET
PR2_MII1_RXER
43
44
PR1_MII0_MT_CLK /
RGMII0_RXC
ENET
3.3 V
I
U5
–
P
0 V
GND
DGND
45
46
PR1_MII0_COL (GPIO5_15)
ENET
3.3 V
I
V1
Y1
I
3.3 V
ENET
PR1_MII0_MR_CLK
(GPIO5_19)
47
48
PR1_MII0_TXD3 /
RGMII0_RXCTL
ENET
3.3 V
I/O
V5
V2
I
3.3 V
ENET
PR1_MII0_RXDV (GPIO5_18)
49
50
DGND
GND
0 V
P
–
U7
I/O
3.3 V
ENET
PR1_MII0_RXER /
RGMII0_TXD2
51
52
PR1_MII0_TXD0 /
RGMII0_RXD0
ENET
3.3 V
I/O
W2
V7
I/O
3.3 V
ENET
PR1_MII0_CRS /
RGMII0_TXD3
53
54
PR1_MII0_TXD1 /
RGMII0_RXD1
ENET
3.3 V
I/O
Y2
U6
I/O
3.3 V
ENET
PR1_MII0_RXD0 /
RGMII0_TXD0
55
56
PR1_MII0_TXD2 /
RGMII0_RXD3
ENET
3.3 V
I/O
V4
V6
I/O
3.3 V
ENET
PR1_MII0_RXD1 /
RGMII0_TXD1
57
58
PR1_MII0_TXEN /
RGMII0_RXD2
ENET
3.3 V
I/O
V3
–
P
0 V
GND
DGND
59
60
DGND
GND
0 V
P
–
W9
I/O
3.3 V
ENET
PR1_MII0_RXD3 /
RGMII0_TXC
61
62
PR2_MII1_RXD[0]
ENET
3.3 V
I
AB5
V9
I/O
3.3 V
ENET
PR1_MII0_RXD2 /
RGMII0_TXCTL
63
64
PR2_MII1_RXD[1]
ENET
3.3 V
I
AB8
U4
I
3.3 V
ENET
PR1_MII0_RXLINK
(GPIO5_16)
65
66
PR2_MII1_RXD[2]
ENET
3.3 V
I
AD6
–
P
0 V
GND
DGND
67
68
PR2_MII1_RXD[3]
ENET
3.3 V
I
AC8
U3
I/O
3.3 V
ENET
RMII_MHZ_50_CLK
69
70
PR2_MII1_TXEN
ENET
3.3 V
O
AB4
–
P
0 V
GND
DGND
71
72
PR2_MII1_TXD[0]
ENET
3.3 V
O
AC6
AC9
I
3.3 V
ENET
PR2_MII1_MR_CLK
73
74
PR2_MII1_TXD[1]
ENET
3.3 V
O
AC7
AC3
I
3.3 V
ENET
PR2_MII1_RXDV
75
76
PR2_MII1_TXD[2]
ENET
3.3 V
O
AC4
AC5
I
3.3 V
ENET
PR2_MII1_MT_CLK
77
78
PR2_MII1_TXD[3]
ENET
3.3 V
O
AD4
–
P
0 V
GND
DGND
79
80
DGND
GND
0 V
P
–
