User's Manual l MBa57xx UM 0100 l © 2020, TQ-Systems GmbH
Page 24
4.2.5
CAN
The two CAN interfaces are designed differently. Depending on the processor version, CAN I can be connected as MCAN and a
maximum of 5 Mbit/s can be transmitted. At the CAN II interface a maximum of 1 Mbit/s can be transmitted.
Illustration 13:
Block diagram CAN
Both TQMa57xx CAN interfaces are connected to CAN transceivers on the MBa57xx and routed to 3-pin connectors X5 and X6.
Both interfaces are galvanically isolated with 1 kV. The CAN interfaces are not galvanically isolated from each other.
The CAN signals can be terminated with 120 Ω using DIP switches S3 and S7.
Table 24:
Pinout CAN1, CAN2
CAN bus
Connector
Pin
Signal
Dir.
Remark
CAN1
CAN2
X5
X6
1
MCAN_HI
I/O
Galvanically isolated
2
MCAN_LO
I/O
Galvanically isolated
3
GND_CAN
P
Galvanically isolated
Table 25:
CAN termination, DIP switches S3, S7
Switch
Signal
ON
OFF
S3-1
MCAN_HI
Terminated with 120 Ω
Not terminated
S3-2
MCAN_LO
Terminated with 120 Ω
Not terminated
S7-1
DCAN2_H
Terminated with 120 Ω
Not terminated
S7-2
DCAN2_L
Terminated with 120 Ω
Not terminated
