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TOSHIBA CORPORATION

TMP96C141AF

➀

Up-counter (UC4/UC5)

UC4/UC5 is a 16-bit binary counter which counts up

according to the input clock specified by T4MOD
<T4CLK1, 0> or T5MOD <T5CLK1, 0> register.

As the input clock, one of the internal clocks

φ

T1 (8/

fc),

φ

T4 (32/fc), and

φ

T16 (128/fc) from 9-bit prescaler

(also used for 8-bit timer), and external clock from TI4 pin
(also used as P80/INT4 pin) or TI6 (also used as P84/
INT6 pin) can be selected. When reset, it will be initialized
to <T4CLK1, 0>/<T5CLK1, 0> = 00 to select TI4/TI6
input mode. Counting or stop and clear of the counter is
controlled by timer operation control register TRUN
<T4RUN, T5RUN>.

When clearing is enabled, up-counter UC4/UC5 will

be cleared to zero each time it coincides matches the

TREG4

TREG5

Upper 8 bits

Lower 8 bits

Upper 8 bits

Lower 8 bits

000031H

000030H

000033H

000032H

TREG6

TREG7

Upper 8 bits

Lower 8 bits

Upper 8 bits

Lower 8 bits

000041H

000040H

000043H

000042H

timer register TREG5, TREG7. The “clear enable/disable”
is set by T4MOD <CLE> and T5MOD <CLE>.

If clearing is disabled, the counter operates as a free-

running counter.

➁

Timer Registers

These two 16-bit registers are used to set the interval

time. When the value of up-counter UC4/UC5 matches
the set value of this timer register, the comparator match
detect signal will be active.

Setting data for timer register (TREG4, TREG5,

TREG6 and TREG7) is executed using 2 byte date trans-
fer instruction or using 1 byte date transfer instruction
twice for lower 8 bits and upper 1 bits in order.

TREG4 and TREG6 timer register is of double buffer

structure, which is paired with register buffer. The timer
control register T45CR <DB4EN, DB6EN> controls
whether the double buffer structure should be enabled or
disabled. : disabled when <DB4EN, DB6EN> = 0, while
enabled when <DB4EN, DB6EN> = 1.

When the double buffer is enabled, the timing to

transfer data from the register buffer to the timer register
is at the match between the up-counter (UC4/UC5) and
timer register TREG5/TREG7.

When reset, it will be initialized to <DB4EN, DB6EN>

= 0, whereby the double buffer is disabled. To use the
double buffer, write data in the timer register, set
<DB4EN, DB6EN> = 1, and then write the following data
in the register buffer.

TREG4, TREG6 and register buffer are allocated to

the same memory addresses 000030H/000031H/
0000400H/000041H. When <DB4EN, DB6EN> = 0,
same value will be written in both the timer register and
register buffer. When <DB4EN, DB6EN> = 1, the value is
written into only the register buffer.

➂

Capture Register

These 16-bit registers are used to hold the values of

the up-counter.

Data in the capture registers should be read by a 2-

byte data load instruction or two 1-byte data load instruc-
tion, from the lower 8 bits followed by the upper 8 bits.

➃

Capture Input Control

This circuit controls the timing to latch the value of

up-counter UC4/UC5 into (CAP1, CAP2)/(CAP3, CAP4).

CAP 1

CAP 2

Upper 8 bits

Lower 8 bits

Upper 8 bits

Lower 8 bits

000035H

000034H

000037H

000036H

CAP 3

CAP 4

Upper 8 bits

Lower 8 bits

Upper 8 bits

Lower 8 bits

000045H

000044H

000047H

000046H

The latch timing of capture register is controlled by regis-
ter T4MOD <CAP12M1, 0>/T5MOD <CAP34M1, 0>.

• When T4MOD <CAP12M1, 0>/T5MOD

<CAP34M1, 0> = 00

Capture function is disabled. Disable is the

default on reset.

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Summary of Contents for TLCS-900 Series

Page 1: ...ltation with TOSHIBA CMOS 16 bit Microcontroller TMP96C141AF 1 Outline and Device Characteristics The TMP96C141AF is high speed advanced 16 bit microcon troller developed for controlling medium to large scale equip ment The TMP96C141AF is housed in an 80 pin flat package Device characteristics are as follows 1 Original 16 bit CPU TLCS 90 instruction mnemonic upward compatible 16M byte linear addre...

Page 2: ...2 TOSHIBA CORPORATION TMP96C141AF Figure 1 TMP96C141AF Block Diagram ...

Page 3: ... Pin Assignment and Functions The assignment of input output pins for TMP96C141AF their name and outline functions are described below Figure 2 1 Pin Assignment 80 pin QFP 2 1 Pin Assignment Figure 2 1 shows pin assignment of TMP96C141AF ...

Page 4: ... Output Port 31 Output port Write Strobe signal for writing data on pins AD0 7 P32 HWR 1 I O Output Port 32 I O port with pull up resistor High write Strobe signal for writing data on pins AD8 15 P33 WAIT 1 I O Input Port 33 I O port with pull up resistor Wait Pin used to request CPU bus wait P34 BUSRQ 1 I O Input Port 34 I O port with pull up resistor Bus request Signal used to request high imped...

Page 5: ...3 4 I O Output Ports 64 67 I O ports that allow selection of I O on a bit basis with pull up resistor Pattern generator ports 10 13 P70 T10 1 I O Input Port 70 I O port with pull up resistor Timer input 0 Timer 0 input P71 T01 1 I O Output Port 71 I O port with pull up resistor Timer output 1 Timer 0 or 1 output P72 T02 1 I O Output Port 72 I O port with pull up resistor PWM output 2 8 bit PWM tim...

Page 6: ... Output Port 90 I O port with pull up resistor Serial send data 0 P91 RXD0 1 I O Input Port 91 I O port with pull up resistor Serial receive data 0 P92 CTS0 1 I O Input Port 92 I O port with pull up resistor Serial data send enable 0 Clear to Send P93 TXD1 1 I O Output Port 93 I O port with pull up resistor Serial send data 1 P94 RXD1 1 I O Input Port 94 I O port with pull up resistor Serial recei...

Page 7: ...set is accepted the CPU sets as follows Program counter PC to 8000H Stack pointer XSP for system mode to 100H SYSM bit of status register SR to 1 Sets to system mode IFF2 to 0 bits of status register to 111 Sets mask register to interrupt level 7 MAX bit of status register to 0 Sets to minimum mode Bits RFP2 to 0 of status register to 000 Sets register banks to 0 When reset is released instruction...

Page 8: ...8 TOSHIBA CORPORATION TMP96C141AF 3 2 Memory Map Figure 3 2 is a memory map of the TMP96C141AF Figure 3 2 Memory Map ...

Page 9: ...to 0 can be changed using the EI instruction con tents of the EI num IFF 2 0 num For example programming EI 3 enables acceptance of maskable interrupts with a priority of 3 or greater and non maskable interrupts which are set in the interrupt controller The DI instruction Interrupts from the CPU 3 Software interrupts privileged violations and Illegal undefined instruction execution Interrupts from...

Page 10: ...10 TOSHIBA CORPORATION TMP96C141AF Figure 3 3 1 Interrupt Processing Flowchart ...

Page 11: ...MHz In maximum mode it is com pleted in 17 states 15 states To return to the main routine after completion of the inter rupt processing the RETI instruction is usually used Executing this instruction restores the contents of the program counter and the status registers Though acceptance of non maskable interrupts cannot be disabled by program acceptance of maskable interrupts can A priority can be...

Page 12: ...it timer 4 TREG4 0 1 4 0 H 8 1 4 0 H 14H 21 INTTR5 16 bit timer 4 TREG5 0 1 5 0 H 8 1 5 0 H 15H 22 INTTR6 16 bit timer 5 TREG6 0 1 6 0 H 8 1 6 0 H 16H 23 INTTR7 16 bit timer 5 TREG7 0 1 7 0 H 8 1 7 0 H 17H 24 INTRX0 Serial receive Channel 0 0 1 8 0 H 8 1 8 0 H 18H 25 INTTX0 Serial send Channel 0 0 1 9 0 H 8 1 9 0 H 19H 26 INTRX1 Serial receive Channel 1 0 1 A 0 H 8 1 A 0 H 1AH 27 INTTX1 Serial sen...

Page 13: ...ns for output A 16M byte space is available for the high speed micro DMA Also in normal mode operation the all address space in other words the space for system mode which is set by the CS WAIT controller can be accessed by high speed micro DMA processing There are two data transfer modes one byte mode and one word mode Incrementing decrementing and fixing the transfer source destination address a...

Page 14: ...ed µDMA cycle of the Transfer Address Increment mode the other mode exe cept the Read only mode is same as this Condition MIN mode 16bit Bus width for 16M Byte 0 wait 2 Register Configuration CPU Control Register These Control Registers cannot be set only LCD cr r instruction ...

Page 15: ...on address space Note n corresponds to high speed µDMA channels 0 3 DMADn DMASn Post increment Increments register value after transfer DMADn DMASn Post decrement Decrement register value after transfer All address space the space for system mode can be accessed by high speed µDMA Do not use undefined codes for transfer mode control ...

Page 16: ...ear bit of the interrupt priority setting register For example to clear the INT0 interrupt request set the register after the as follows INTE0AD 0 Zero clears the INT0 Flip Flop The status of the interrupt request flip flop is detected by reading the clear bit Detects whether there is an interrupt request for an interrupt channel The interrupt priority can be set by writing the priority in the int...

Page 17: ...TOSHIBA CORPORATION 17 TMP96C141AF Figure 3 3 3 1 Block Diagram of Interrupt Controller ...

Page 18: ...18 TOSHIBA CORPORATION TMP96C141AF 1 Interrupt Priority Setting Register ...

Page 19: ...TOSHIBA CORPORATION 19 TMP96C141AF 2 External Interrupt Control ...

Page 20: ... an inter rupt it simultaneously compares the interrupt vector with each channel s micro DMA start vector bits 4 to 8 of the interrupt vec tor When both match the interrupt is processed in micro DMA mode for the channel whose value matched If the interrupt vector matches more than one chan nel the channel with the lower channel number has a higher priority 4 Notes The instruction execution unit an...

Page 21: ...fc Standby mode 00 RUN mode 01 STOP mode 10 IDLE mode 11 Don t care 1 Connects watchdog timer output to RESET pin internally 1 Drive pin even in STOP mode Standby Release by Interrupt Interrupt Level Standby Mode Interrupt Mask IFF2 to 0 Interrupt Request Level Interrupt Mask IFF2 to 0 Interrupt Request Level RUN Can be released by any interrupt After standby mode is released interrupt processing ...

Page 22: ... depends on the output function data If a pin is also used for an input function whether pull up or pull down is selected depends on the port register setting value only Table 3 4 1 Pin States in STOP Mode Pin Name I O 96C141AF 96CM40 96PM40 DRVE 0 DRVE 1 DRVE 0 DRVE 1 P0 Input mode AD0 7 Output mode x x Output P1 Input mode AD8 15 Output mode A8 15 x x Output P2 Input mode Output mode A0 7 A16 23...

Page 23: ...ction Port0 P00 P07 8 I O Bit AD0 AD7 Port1 P10 P17 8 I O Bit AD8 AD15 A8 A15 Port2 P20 P27 8 I O Bit A0 A7 A16 A23 Port 3 P30 P31 P32 P33 P34 P35 P36 P37 1 1 1 1 1 1 1 1 Output Output I O I O I O I O I O I O Fixed Fixed Bit Bit Bit Bit Bit Bit RD WR HWR WAIT BUSRQ BUSAK R W RAS Port4 P40 P41 P42 1 1 1 I O I O I O Bit Bit Bit CS0 CAS0 CS1 CAS1 CS2 CAS2 Port5 P50 P53 4 Input Fixed AN0 AN3 Port6 P60...

Page 24: ...istor of pull up That is when it is used for bus release BUSAK 0 the pins of below need pull up or pull down resistor for an external circuit P00 P07 AD07 P10 P17 AD8 AD15 P30 RD P31 WR When the bus is released both internal memory and internal I O cannot be accessed But the internal I O continues to run Therefore be careful about releasing time and set the setection time WDT Resetting makes the p...

Page 25: ... 1 always functions as an address data bus AD8 to 15 regardless of the value set in control reg ister P1CR 3 5 1 Port 0 P00 P07 Port 0 is an 8 bit general purpose I O port I O can be set on a bit basis using control register P0CR to 0 and sets Port 0 to input mode In addition to functioning as a general purpose I O port Port 0 also functions as an address data bus AD0 to 7 To access external memor...

Page 26: ...26 TOSHIBA CORPORATION TMP96C141AF Port 0 Register Figure 3 5 3 Registers for Ports 0 and 1 ...

Page 27: ...esetting resets all bits of output latch P2 control regis ter P2CR and function register P2FC to 0 It also sets Port 2 to input mode and connects a pull down resistor To disconnect the pull down resistor write 1 in the output latch In addition to functioning as a general purpose I O port Port 2 also functions as an address data bus A0 to 7 and an address bus A16 to 23 Figure 3 5 4 Port 2 ...

Page 28: ...28 TOSHIBA CORPORATION TMP96C141AF Figure 3 5 5 Registers for Port 2 ...

Page 29: ...stor In addition to functioning as a general purpose I O port Port 3 also functions as an I O for the CPU s control status sig nal With the TMP96C141AF when P30 pin is defined as RD signal output mode P30F 1 clearing the output latch register P30 to 0 outputs the RD strobe used for the pseudo static RAM from the P30 pin even when the internal address area is accessed If the output latch register P...

Page 30: ...30 TOSHIBA CORPORATION TMP96C141AF Figure 3 5 6 Port 3 P30 P31 P32 P35 P36 P37 ...

Page 31: ...TOSHIBA CORPORATION 31 TMP96C141AF Figure 3 5 7 Port 3 P33 P34 ...

Page 32: ...32 TOSHIBA CORPORATION TMP96C141AF Port 3 Register Note When P33 WAIT pin is used as a WAIT pin set P CR P33C to 0 and Chip Select Wait control register Figure 3 5 8 Registers for Port 3 ...

Page 33: ...ets the P40 and P42 output latch registers to 1 Resets all bits of the P42 output latch register the control register P4CR and the function register P4FC to 0 Sets P40 and P41 to input mode and connects a pull up resistor Sets P42 to input mode and connects a pull down resistor In addition to functioning as a general purpose I O port Port 4 also functions as a chip select output signal CS0 to CS2 ...

Page 34: ...34 TOSHIBA CORPORATION TMP96C141AF Figure 3 5 9 Port 4 ...

Page 35: ...ip select signal CS0 CAS0 to CS2 CAS2 set the corresponding bits of the control register P4CR and the function register to P4FC The BOCS B1CS and B2CS registers of the chip select wait controller are used to select the CS CAS function Figure 3 5 10 Registers for Port 4 ...

Page 36: ...also used as an analog input pin Figure 3 5 11 Port 5 Note The input channel selection of A D Converter is set by A D Converter mode register ADMOD2 Figure 3 5 12 Registers for Port 5 Port 5 Register 7 6 5 4 3 2 1 0 bit Symbol P53 P52 P51 P50 Read Write R After reset Input mode P5 000DH ...

Page 37: ... also sets all bits of the output latch to 1 In addition to functioning as a general purpose I O port Port 6 also functions as a pattern generator PG0 PG1 output PG0 is assigned to P60 to P63 PG1 to P64 to P67 Writing 1 in the corresponding bit of the port 6 function register P6FC enables PG output Resetting resets the function register P6FC value to 0 and sets all bits to ports Figure 3 5 13 Port...

Page 38: ...38 TOSHIBA CORPORATION TMP96C141AF Port 6 Register Figure 3 5 14 Registers for Port 6 ...

Page 39: ...ition to functioning as a general purpose I O port Port 70 also functions as an input clock pin TI0 Port 71 as an 8 bit timer output TO1 Port 72 as a PWM0 output TO2 and Port 73 as a PWM1 output TO3 pin Writing 1 in the corresponding bit of the Port 7 function register P7FC enables output of the timer Resetting resets the function regis ter P7FC value to 0 and sets all bits to ports Figure 3 5 15 ...

Page 40: ...40 TOSHIBA CORPORATION TMP96C141AF Figure 3 5 16 Registers for Port 7 ...

Page 41: ...ut latch register P8 to 1 In addition to functioning as a general purpose I O port Port 8 also functions as an input for 16 bit timer 4 and 5 clocks an output for 16 bit timer F F 4 5 and 6 output and an input for INT0 Writing 1 in the corresponding bit of the Port 8 function register P8FC enables those functions Resetting resets the function register P8FC value to 0 and sets all bits to ports 1 P...

Page 42: ...42 TOSHIBA CORPORATION TMP96C141AF 2 P87 INT0 Port 87 is a general purpose I O port and also used as an INT0 pin for external interrupt request input Figure 3 5 18 Port 87 ...

Page 43: ...TOSHIBA CORPORATION 43 TMP96C141AF Figure 3 5 19 Registers for Port 8 ...

Page 44: ... to functioning as a general purpose I O port Port 9 can also function as an I O for serial channels 0 and 1 Writing 1 in the corresponding bit of the port 9 function register P9FC enables this function Figure 3 5 20 Ports 90 and 93 Resetting resets the function register value to 0 and sets all bits to ports 1 Port 90 and 93 TXD0 TXD1 Ports 90 and 93 also function as serial channel TXD output pins...

Page 45: ... 94 are I O ports and also used as RXD input pins for serial channels Figure 3 5 21 Ports 91 and 94 3 Port 92 CTS SCKL0 Port 92 is an I O port It is also used as a CTS input pin for serial channel0 additionally the CTS0 pin and also as a SCKL0 I O pin Figure 3 5 22 Port 92 ...

Page 46: ...46 TOSHIBA CORPORATION TMP96C141AF 4 Port 95 SCLK Port 95 is a general purpose I O port It is also used as an SCLK I O pin for serial channel 1 Figure 3 5 23 Port 95 ...

Page 47: ...TOSHIBA CORPORATION 47 TMP96C141AF Figure 3 5 24 Registers for Port 9 ...

Page 48: ...ting clears bit 5 to 0 4 Data bus size select Bit 4 B0BUS B1BUS and B2BUS of the control reg ister is used to specify data bus size Setting this bit to 0 accesses the memory in 16 bit data bus mode set ting it to 1 accesses the memory in 8 bit data bus mode Changing data bus size depending on the access address is called dynamic bus sizing Table 3 6 2 shows the details of the bus operation 5 Wait ...

Page 49: ...IT n 11 0WAIT 00 7F00H 7FFFH 01 400000H 10 800000H 11 C00000H B1CS Block1 CS WAIT control register 0069H B1E B1SYS B1CAS B1BUS B1W1 B1W0 B1C1 B1C0 W W W W W W W W 0 0 0 0 0 0 0 0 1 CS CAS Enable 1 SYSTEM only 0 CS1 1 CAS1 0 16 bit Bus 1 8 bit Bus 00 2WAIT 01 1WAIT 10 1WAIT n 11 0WAIT 00 480H 7FFFH 01 400000H 10 800000H 11 C00000H B2CS Block2 CS WAIT control register 006AH B2E B2SYS B2CAS B2BUS B2W...

Page 50: ...2n 1 odd number 8 bits 2n 1 xxxxx b7 b0 16 bits 2n 1 b7 b0 xxxxx 16 bits 2n 0 even number 8 bits 2n 0 2n 1 xxxxx xxxxx b7 b0 b15 b8 16 bits 2n 0 b15 b8 b7 b0 2n 1 odd number 8 bits 2n 1 2n 2 xxxxx xxxxx b7 b0 b15 b8 16 bits 2n 1 2n 2 b7 b0 xxxxx xxxxx b15 b8 32 bits 2n 0 even number 8 bits 2n 0 2n 1 2n 2 2n 3 xxxxx xxxxx xxxxx xxxxx b7 b0 b15 b8 b23 b16 b31 b24 16 bits 2n 0 2n 2 b15 b8 b31 b24 b7 ...

Page 51: ...t specify the same address area more than once However when addresses 7F00H 7FFFH for CS0 and 480H 7FFFH for CS1 are specified in other words specifications overlap only the CS0 setting pin is active CS0 CS1 CS2 000000H 7F00H B1C1 0 00 8000H B0C1 0 00 400000H B2C1 0 00 800000H B0C1 0 01 B1C1 0 01 B2C1 0 01 C00000H B0C1 0 10 B1C1 0 10 B2C1 0 10 FFFFFFH B0C1 0 11 B1C1 0 11 B2C1 0 11 Mainly for I O M...

Page 52: ...n ROM 16 bits RAM and I O 8 bits Resetting sets pins CS0 to CS2 to input port mode CS0 and CS1 are set high due to an internal pull up resistor CS2 low due to an internal pull down resistor The program used to set these pins is as follows P4CR EQU 0EH P4FC EQU 10H B0CS EQU 68H B1CS EQU 69H B2CS EQU 6AH LD BOCS 90H CS0 8 bits 2WAIT 7F00H 7FFFH LD B1CS 9CH CS1 8 bits 0WAIT 480H 7EFFH LD B2CS 84H CS2...

Page 53: ... 9CH CS2 8 bit 0WAIT 8000H After reset the program reads the LDX B2CS 9CH instruction in 16 bit data bus mode LDX is a 6 byte instruc tion the 2nd 4th and 6th bytes are handled as dummies i e only codes in the 1st 3rd and 5th bytes are actually used Even if starting in 8 bit data bus mode it is possible to pro gram so that the LDX instruction is executed and the block 2 area 8000H 3FFFFFH is acces...

Page 54: ...e cycle output mode 1 timer 8 bit pulse width modulation PWM variable duty with con stant cycle output mode 1 timer Figure 3 7 1 shows the block diagram of 8 bit timer timer 0 and timer 1 Each interval timer consists of an 8 bit up counter 8 bit comparator and 8 bit timer register Besides one timer flip flop TFF1 is provided for pair of timer 0 and timer 1 Among the input clock sources for the int...

Page 55: ...TOSHIBA CORPORATION 55 TMP96C141AF Figure 3 7 1 Block Diagram of 8 Bit Timers Timers 0 and 1 ...

Page 56: ...fc according to the set value of TMOD register The input clock of timer 1 differs depending on the operation mode When set to 16 bit timer mode the overflow output of timer 0 is used as the input clock When set to any other mode than 16 bit timer mode the input clock is selected from the internal clocks φ T1 8 fc φ T16 128 fc and φT256 2048 fc as well as the comparator output match detection signa...

Page 57: ...is transferred from the register buffer to the timer regis ter when the 2n 1 overflow occurs in PWM mode or at the PPG cycle in PPG mode Therefore during timer mode the double buffer cannot be used When reset it will be initialized to DBEN 0 to dis able the double buffer To use the double buffer write data in the timer register set DBEN to 1 and write the following data in the register buffer The ...

Page 58: ...58 TOSHIBA CORPORATION TMP96C141AF Figure 3 7 4 Timer Operation Control Register TRUN ...

Page 59: ...TOSHIBA CORPORATION 59 TMP96C141AF Figure 3 7 5 Timer Mode Control Register TMOD ...

Page 60: ...60 TOSHIBA CORPORATION TMP96C141AF Figure 3 7 6 Timer Flip Flop Control Register TFFCR ...

Page 61: ...EG1 0 1 0 1 0 0 0 0 Set the timer register at 40µs φT1 50H INTET10 1 1 0 1 Enable INTT1 and set it to Level 5 TRUN 1 x 1 Start timer 1 counting Table 3 7 1 8 Bit Timer Interrupt Cycle and Input Clock Input Clock Interrupt Cycle at fc 16MHz Resolution Interrupt Cycle at fc 20MHz Resolution φT1 8 fc 0 5µs 128µs 0 5µs 0 4µs 102 4µs 0 4µs φT4 32 fc 2µs 512µs 2µs 1 6µs 409 6µs 1 6µs φT16 128 fc 8µs 2 0...

Page 62: ... timer 1 may be used but this example uses timer 1 Note x don t care no change Figure 3 7 7 Square Wave 50 Duty Output Timing Chart 7 6 5 4 3 2 1 0 TRUN x 0 Stop timer 1 and clear it to 0 TMOD 0 0 x x 0 1 Set the 8 bit timer mode and select φT1 0 5µs fc 16MHz as the input clock TREG1 0 0 0 0 0 0 1 1 Set the timer register at 3 0µs φT1 2 3 TFFCR 1 0 1 1 Clear TFF1 to 0 and set to invert by the matc...

Page 63: ...FFCR TFF1C1 0 to set TFF1 to 1 Table 3 7 2 16 Bit Timer Interrupt and Input Clock Input Clock Interrupt Cycle at fc 16MHz Resolution Interrupt Cycle at fc 20MHz Resolution φT1 8 fc 0 5µs 32 786ms 0 5µs 0 4µs 26 214ms 0 4µs φT4 32 fc 2µs 131 072ms 2µs 1 6µs 104 857ms 1 6µs φT16 128 fc 8µs 524 288ms 8µs 6 4µs 419 430ms 6 4µs Note The value of timer register cannot be read 2 16 bit timer mode A 16 bi...

Page 64: ...es match When the match detect signal is output simultaneously from both com parators of timer 0 and timer 1 the up counters UC0 and UC1 are cleared to 0 and the interrupt INTT1 is generated If inversion is enabled the value of the timer flip flop TFF1 is inverted Example When TREG1 04H and TREG0 80H Figure 3 7 9 Output Timer by 16 Bit Timer Mode 3 8 bit PPG Programmable Pulse Generation Output mo...

Page 65: ...TOSHIBA CORPORATION 65 TMP96C141AF Figure 3 7 10 8 Bit PPG Output Waveforms Figure 3 7 11 Block Diagram of 8 Bit PPG Output Mode ...

Page 66: ...50KHz 20µs Given φ T1 0 5µs 16MHz 20µs 0 5µs 40 Consequently to set the timer register 1 TREG1 to TREG1 40 28H and then duty to 1 4 t x 1 4 20µs x 1 4 5µs 5µs 0 5µs 10 Therefore set timer register 0 TREG0 to TREG0 10 0AH Note x don t care no change 7 6 5 4 3 2 1 0 TRUN x 0 0 Stop timer 0 and clear it to 0 TMOD 1 0 x x x x 0 1 Set the 8 bit PPG mode and select φT1 as input clock TREG0 0 0 0 0 1 0 1...

Page 67: ...nverted when up counter UC0 matches the set value of timer register TREG0 or when 2n 1 n 6 7 or 8 specified by T01MOD PWM01 Figure 3 7 13 8 Bit PWM Waveforms 0 counter overflow occurs Up counter UC0 is cleared when 2n 1 counter overflow occurs For example when n 6 6 bit PWM will be output while when n 7 7 bit PWM will be output To use this PWM mode the following conditions must be satisfied Set va...

Page 68: ...when the double buffer of TREG0 is enabled Use of the double buffer makes the handling of small duty waves easy Figure 3 7 15 Operation of Register Buffer Example To output the following PWM waves to TO1 pin at fc 16MHz To realize 63 5µs of PWM cycle by φT1 0 5µs fc 16MHz 63 5µs 0 5µs 127 27 1 Consequently n should be set to 7 As the period of low level is 36µs for φT1 0 5µs set the following valu...

Page 69: ...µsec 15 7kHz 254msec 3 9kHz 1 01µsec 0 98kHz 50 8µsec 19 7kHz 203µsec 4 9kHz 0 81msec 1 2kHz 28 1 127µsec 7 8kHz 510msec 1 9kHz 2 04µsec 0 49kHz 102µsec 9 80kHz 408µsec 2 4kHz 1 63msec 0 61kHz Table 3 7 4 Timer Mode Setting Registers Register Name TMOD TFFCR Name of Function in T10M PWMM T1CLK T0CLK TFF1IS Function Timer Mode PWM0 Cycle Upper Timer Input Clock Lower Timer Input Clock Timer F F Inv...

Page 70: ...t interval timer mode Figure 3 8 1 is a block diagram of 8 bit PWM timer tim ers 2 and 3 PWM timers consist of an 8 bit up counter 8 bit com parator and 8 bit timer register Two timer flip flops TFF2 for timer 2 and TFF3 for timer 3 are provided Input clocks φP1 φP4 and φP16 for the PWM timers can be obtained using the built in prescaler PWM timer operating mode and timer flip flops are con trolle...

Page 71: ...TOSHIBA CORPORATION 71 TMP96C141AF Figure 3 8 1 Block Diagram of 8 Bit PWM Timer 0 Timer 2 Note Block diagram for 8 bit PWM timer 1 timer 3 is the same as the above diagram ...

Page 72: ... which counts up using the input clock specified by PWM mode register P0MOD or P1MOD The input clock for the PWM0 PWM1 is selected from the internal clocks φP1 φP4 and φP16 PWM dedi cated prescaler output depending on the value set in the P0MOD P1MOD register Operating mode is also set by P0MOD and P1MOD registers At reset they are initialized to P0MOD PWM0M 0 and P1MOD PWM1M 0 thus the up counter...

Page 73: ...ame value is written to both register buffer and timer register When DB2EN DB3EN 1 the value is written to the register buffer only Memory addresses of the timer registers are as follows TREG2 000026H TREG3 000027H Both timer registers are write only however register buffer values can be read when reading the above addresses Comparator Compares the value in the up counter with the value in the tim...

Page 74: ...74 TOSHIBA CORPORATION TMP96C141AF Figure 3 8 4 8 Bit PWM0 Mode Control Register ...

Page 75: ...TOSHIBA CORPORATION 75 TMP96C141AF Figure 3 8 5 8 Bit PWM1 Mode Control Register ...

Page 76: ...76 TOSHIBA CORPORATION TMP96C141AF Figure 3 8 6 8 Bit PWM F F Control Register ...

Page 77: ...TOSHIBA CORPORATION 77 TMP96C141AF Figure 3 8 7 Timer Operation Control Register TRUN ...

Page 78: ...Note The above waves are obtained in a mode where the F F is set by a match with the timer register TREG and reset by an overflow Condition 2 TFF2 is set to 1 when the value in the up counter UC2 and the value set in TREG2 match TFF2 is cleared to 0 when a 2n 1 counter over flow n 6 7 or 8 occurs The up counter UC2 is cleared by a 2n 1 counter overflow The PWM timer can output 0 100 duty pulses be...

Page 79: ...9 Block Diagram of PWM Timer Mode PWM0 In this mode enabling double buffer is very useful The register buffer value shifts into TREG2 when a 2n 1 overflow is detected when double buffer is enabled Using double buffer makes handling small duty waves easy Figure 3 8 10 Register Buffer Operation ...

Page 80: ...ffer TREG2 0 0 1 1 1 1 0 0 Writes 3CH P0MOD 1 0 0 0 0 0 1 Enables double buffer PFFCR 0 1 1 1 Sets TFF2 and a mode where TFF2 is set by compare and match and cleared by overflow P7CR x x x x 1 P7FC x x x x 1 x TRUN 1 x 1 Starts PWM0 counting Table 3 8 1 PWM Cycle and 2n 1 Counter Setting Formula 16MHz 20MHz φP1 φP4 φP16 φP1 φP4 φP16 26 1 26 1 φPn 15 8µsec 63kHz 63 0µsec 16kHz 252µsec 3 9kHz 12 6µs...

Page 81: ... 0 Sets 40µs 0 25µs A0H in timer register INTEPW10 1 1 0 0 Enables INTT2 and sets interrupt level 4 TRUN 1 x 1 Starts PWM0 counting Table 3 8 2 Interrupt Cycle and Input Clock Selection using 8 Bit Timer Mode Input Clock Interrupt Cycle at fc 16MHz Resolution Interrupt Cycle at fc 20MHz Resolution φP1 4 fc 0 25µs 64µs 0 25µs 0 2µs 51 2µs 0 2µs φP4 16 fc 1µs 256µs 1µs 0 8µs 204 8µs 0 8µs φP16 64 fc...

Page 82: ...om TO2 pin set register as fol lows Note x don t care no change Figure 3 8 11 Square Wave 50 Duty Output Timing Chart 7 6 5 4 3 2 1 0 TRUN x 0 Stops PWM0 and clears it to 0 P0MOD x 0 1 1 0 0 x x Sets 8 bit timer mode and selects φP1 0 25µs as the input clock TREG2 0 0 0 0 0 1 1 0 Sets 3 0µs 0 25µs 2 6 in the timer register PFFCR 1 0 0 1 Clears TFF2 to 0 and inverts using comparator output P7CR x x...

Page 83: ...TOSHIBA CORPORATION 83 TMP96C141AF This mode is as shown in Figure 3 8 12 below Figure 3 8 12 Block Diagram of 8 Bit Timer Mode ...

Page 84: ...ment mode Pulse width measurement mode Time differential measurement mode Timer event counter consists of 16 bit up counter two 16 bit timer registers two 16 bit capture registers one of them applies double buffer two comparators capture input con troller and timer flip flop and the control circuit Timer event counter is controlled by four control regis ters T4MOD T5MOD T4FFCR T5FFCR TRUN and T45C...

Page 85: ...TOSHIBA CORPORATION 85 TMP96C141AF Figure 3 9 1 Block Diagram of 16 Bit Timer Timer 4 ...

Page 86: ...86 TOSHIBA CORPORATION TMP96C141AF Figure 3 9 2 Block Diagram of 16 Bit Timer Timer 5 ...

Page 87: ...TOSHIBA CORPORATION 87 TMP96C141AF Figure 3 9 3 16 Bit Timer Mode Controller Register T4MOD 1 2 ...

Page 88: ...88 TOSHIBA CORPORATION TMP96C141AF Figure 3 9 4 16 Bit Controller Register T4MOD 2 2 ...

Page 89: ...TOSHIBA CORPORATION 89 TMP96C141AF Figure 3 9 5 16 Bit Timer 4 F F Control T4FFCR ...

Page 90: ...90 TOSHIBA CORPORATION TMP96C141AF Figure 3 9 6 16 Bit Timer Mode Control Register T5MOD 1 2 ...

Page 91: ...TOSHIBA CORPORATION 91 TMP96C141AF Figure 3 9 7 16 Bit Timer Control Register T5MOD 2 2 ...

Page 92: ... 3 9 8 16 Bit Timer 5 F F Control T5FFCR CAP4T6 Invert when the up counter value is loaded to CAP4 CAP3T6 Invert when the up counter value is loaded to CAP3 EQ7T6 Invert when up counter matches TREG7 EQ6T6 Invert when up counter matches TREG6 ...

Page 93: ...OSHIBA CORPORATION 93 TMP96C141AF Figure 3 9 9 16 Bit Timer Timer 4 5 Control Register T45CR Figure 3 9 10 Timer Operation Control Register TRUN DB6EN Double buffer of TREG6 DB4EN Double buffer of TREG4 ...

Page 94: ...timer register is of double buffer structure which is paired with register buffer The timer control register T45CR DB4EN DB6EN controls whether the double buffer structure should be enabled or disabled disabled when DB4EN DB6EN 0 while enabled when DB4EN DB6EN 1 When the double buffer is enabled the timing to transfer data from the register buffer to the timer register is at the match between the ...

Page 95: ...4T4 T6FFCR CAP4T6 CAP3T6 EQ7T6 EQ6T6 TFF4 TFF6 will be inverted when 00 is written in T4FFCR TFF4C1 0 T6FFCR TFF6C1 0 Also it is set to 1 when 10 is written and cleared to 0 when 10 is written The value of TFF4 TFF6 can be output to the timer output pin TO4 also used as P82 and TO6 also used as P86 Timer Flip Flop TFF5 This flip flop is inverted by the match detect signal from the comparator and t...

Page 96: ...set the prescaler in RUN mode 7 6 5 4 3 2 1 0 TRUN x 0 Stop timer 4 P8CR 0 Set P80 to input mode INTET54 1 1 0 0 1 0 0 0 Enable INTTR5 and sets interrupt level 4 while disables INTTR4 T4FFCR 1 1 0 0 0 0 1 1 Disable trigger T4MOD 0 0 1 0 0 1 0 0 Select TI4 as the input clock TREG5 Set the number of counts 16 bits TRUN 1 x 1 Start timer 4 Assign P82 as TO4 3 16 bit Programmable Pulse Generation PPG ...

Page 97: ...bled in this mode the value of register buffer 4 will be shifted in TREG4 at match with TREG5 This feature makes easy the handling of low duty waves Figure 3 9 12 Operation of Register Buffer Shows the block diagram of this mode Figure 3 9 13 Block Diagram of 16 Bit PPG Mode ...

Page 98: ...Pulse Output with Delay One Shot Pulse Output from External Trigger Pulse Set the up counter UC4 in free running mode with the internal input clock input the external trigger pulse from TI4 pin and load the value of up counter into capture register CAP1 at the rise edge of the TI4 pin Then set to T4MOD CAP12M1 0 01 When the interrupt INT4 is generated at the rise edge of TI4 input set the CAP1 val...

Page 99: ... x 1 Start timer 4 Setting of INT4 TREG4 CAP1 3ms φT1 TREG5 TREG4 2ms φT1 T4FFCR 1 1 Enable TFF4 inversion when the up counter value matches TREG4 or 5 INTET54 1 1 0 0 Enable INTTR5 Setting of INT5 T4FFCR 0 0 Disable TFF4 inversion when the up counter value matches TREG 4 or 5 INTET54 1 0 0 0 Disable INTTR5 Select P82 as the TO4 pin When delay time is unnecessary invert timer flip flop TFF4 when t...

Page 100: ...t clock of Timer 4 The value of the up counter is loaded Figure 3 9 16 Frequency Measurement For example if the value for the level 1 width of TFF1 of the 8 bit timer is set to 0 5 sec and the differ ence between CAP1 and CAP2 is 100 the frequency will be 100 0 5 sec 200 Hz into the capture register CAP1 at the rise edge of the timer flip flop TFF1 of 8 bit timers Timer 0 and Timer 1 and into CAP2...

Page 101: ...idth Measurement Note Only in this pulse width measuring mode T4MOD CAP12M1 0 10 external interrupt INT4 occurs at the falling edge of TI4 pin input In other modes it occurs at the rising edge The width of L level can be measured from the dif ference between the first C2 and the second C1 at the second INT4 interrupt Time Difference Measurement This mode is used to measure the difference in time b...

Page 102: ... by free running up counter UC4 When the value in up counter UC4 and the value in TREG4 TREG5 match the value in TFF4 TFF5 is inverted and output to TO4 TO5 This mode can only be used by 16 bit timer 4 Figure 3 9 19 Phase Output Cycles counter overflow time of the above output waves are listed below 16MHz 20MHz φT1 1 024msec 0 819msec φT4 4 096msec 3 277msec φT16 16 38 msec 13 11 msec ...

Page 103: ... 0 PG0 is synchronous with 8 bit timer 0 or timer 1 16 bit timer 5 to update the output The PG ports are controlled by control registers PG01CR and can select either stepping motor control mode or pattern generation mode Each bit of the P6 can be used as the PG port PG0 and PG1 can be used independently All PG operate in the same manner except the following points and thus only the operation of PG...

Page 104: ...104 TOSHIBA CORPORATION TMP96C141AF Figure 3 10 2a Pattern Generation Control Register PG01CR ...

Page 105: ...TOSHIBA CORPORATION 105 TMP96C141AF Figure 3 10 2b Pattern Generation Control Register PG01CR ...

Page 106: ...ster Reading the P6 that is set to the PG port allows to read out Shift alternate register 0 For the PG mode 4 bit write register 7 6 5 4 3 2 1 0 bit Symbol PG13 PG12 PG11 PG10 SA13 SA12 SA11 SA10 Read Write W R W After reset 0 0 0 0 Undefined Function Pattern Generation 1 PG1 output latch register Reading the P6 that is set to the PG port allows to read out Shift alternate register 1 For the PG m...

Page 107: ...TOSHIBA CORPORATION 107 TMP96C141AF Figure 3 10 5 16 bit Timer Trigger Control Register T45CR ...

Page 108: ...should be done during the interrupt operation of the timer for shift trigger and a pattern can be output synchronous with the timer In this mode set PG01CR PG0M and PG1M to 1 and PG01CR CCW0 and CCW1 to 0 The output of this pattern generator is output to port 6 since port and functions can be switched on a bit basis using port function control register P6FC any port pin can be assigned to pattern ...

Page 109: ...trigger from timer In this pattern generation mode only writing the output latch is disabled by hardware but other functions do the same operation as 1 2 excitation in stepping motor control port mode Accordingly the data shifted by trigger signal from a timer must be written before the next trigger signal is output ...

Page 110: ... 4 phase 1 excitation and 4 phase 2 excita tion respectively when channel 0 PG0 is selected Note bn indicates the initial value of PG0REG b7 b6 b5 b4 x x x x Normal Rotation Reverse Rotation Figure 3 10 8 Output Waveforms of 4 Phase 1 Step Excitation Normal Rotation and Reverse Rotation Initial value of PG0REG 0100 x x x x Initial value of PG0REG 0100 x x x x ...

Page 111: ... specified by PG01CR CCW0 Normal rotation PG00 PG01 PG02 PG03 when CCW0 is set to 0 reverse rotation PG00 PG01 PG02 PG03 when 1 Four phase 1 step excitation will be selected when only one bit is set to 1 during the initialization of PG while 4 phase 2 step excitation will be selected when two consecutive bits are set to 1 The value in the shift alternate registers are ignored when the 4 phase 1 st...

Page 112: ...se 1 2 step excitation when channel 0 is selected Note bn denotes the initial value of PG0REG b7 b6 b5 b4 b3 b2 b1 b0 Normal Rotation Reverse Rotation Figure 3 10 11 Output Waveforms of 4 Phase 1 2 Step Excitation Normal Rotation and Reverse Rotation Initial value of PG0REG 11001000 Initial value of PG0REG 10001100 ...

Page 113: ...t waveform of negative logic set val ues 1s and 0 s of the initial value should be inverted For example to change the output waveform shown in Fig ure 3 10 11 into negative logic change the initial value to 00110111 The operation will be explained below for channel 0 The output latch of PG0 shared by P6 and the shifter alternate register SA0 for Pattern Generation are shifted at the rising edge of...

Page 114: ... or TREG1 value 16 bit timer mode When the up counter value matches with both TREG0 and TREG1 values The value of up counter TREG1 28 TREG0 PPG output mode When the up counter value matches with both TREG0 and TREG1 When the up counter value matches TREG1 value PPG cycle PWM output mode When the up counter value matches TREG0 value and PWM cycle Trigger signal for PG is not generated 3 Trigger Sig...

Page 115: ... 0 0 0 1 Set PG0 in 4 phase 1 step excitation mode PG0REG Set an initial value TRUN 1 x 1 1 Start timer 0 and timer 1 4 Application of PG and Timer Output As explained in Trigger signal from timer the timing to shift PG and invert TFF differs depending on the mode of timer An application to operate PG while operating an 8 bit timer in PPG mode will be explained below To drive a stepping motor in a...

Page 116: ...ignal SCLK for extending I O Mode 1 7 bit data Asynchronous transmission Mode 2 8 bit data UART mode channel 0 and 1 Mode 3 9 bit data Note TMP96C141AF TMP96C041AF TMP96CM40F TMP96PM40F with Channel 0 and 1 In mode 1 and mode 2 a parity bit can be added Mode 3 has wake up function for making the master controller start slave controllers in serial link multi controller system Figure 3 11 1 shows th...

Page 117: ...mode a check function is added not to start the receiving operation by error start bits due to noise The channel starts receiving data only when the start bit is detected to be normal at least twice in three samplings When the transmission buffer becomes empty and requests the CPU to send the next transmission data or when data is stored in the receiving data register and the CPU is requested to r...

Page 118: ...118 TOSHIBA CORPORATION TMP96C141AF Note There is SC1MOD 56H in Channel 1 Figure 3 11 2 Serial Mode Control Register Channel 0 SC0MOD ...

Page 119: ...TMP96C141AF Note Serial control register for channel 1 is SC1CR 55H As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 11 3 Serial Control Register Channel SC0CR ...

Page 120: ...a single bit with a bit testing instruction Figure 3 11 4 Serial Channel Control Channel 0 BR0CR Figure 3 11 5 Serial Transmission Receiving Buffer Registers Channel 0 SC0BUF 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Transmission Receiving SC0BUF 50H ...

Page 121: ...TOSHIBA CORPORATION 121 TMP96C141AF Figure 3 11 6 Serial Mode Control Register Channel 1 SC1MOD ...

Page 122: ...122 TOSHIBA CORPORATION TMP96C141AF Note As all error flags are cleared after reading do not test only a single bit with a bit testing instruction Figure 3 11 7 Serial Control Register Channel 1 SC1CR ...

Page 123: ...e prescaler in RUN mode Figure 3 11 8 Baud Rate Generator Control Register Channel 0 BR0CR Figure 3 11 9 Serial Transmission Receiving Buffer Registers Channel 1 SC1BUF 7 6 5 4 3 2 1 0 TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 7 6 5 4 3 2 1 0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 Transmission Receiving SC1BUF 0054H ...

Page 124: ...124 TOSHIBA CORPORATION TMP96C141AF Figure 3 11 10 Port 9 Function Register P9FC Port 3 11 11 Port 9 Open Drain Enable Register ODE ...

Page 125: ...TOSHIBA CORPORATION 125 TMP96C141AF 3 11 2 Configuration Figure 3 11 12 shows the block diagram of the serial channel 0 Figure 3 11 12 Block Diagram of the Serial Channel 0 ...

Page 126: ...126 TOSHIBA CORPORATION TMP96C141AF Figure 3 11 13 shows the block diagram of the serial channel 1 Figure 3 11 13 Block Diagram of the Serial Channel 1 ...

Page 127: ...n of Transfer Rate 1 When Baud Rate Generator is Used Unit kbps fc Mhz Input Clock Frequency Divisor φT0 fc 4 φT2 fc 16 φT8 fc 64 φT32 fc 256 9 830400 2 76 800 19 200 4 800 1 200 4 38 400 9 600 2 400 0 600 8 19 200 4 800 1 200 0 300 0 9 600 2 400 0 600 0 150 12 288000 5 38 400 9 600 2 400 0 600 A 19 200 4 800 1 200 0 300 14 745600 3 76 800 19 200 4 800 1 200 6 38 400 9 600 2 400 0 600 C 19 200 4 8...

Page 128: ...R SCLKC regis ter to generate the basic clock 2 Asynchronous Communication UART mode According to the setting of SC0CR and SC1CR SC1 0 the above baud rate gen erator clock internal clock φ1 500 Kbps fc 16 MHz or the match detect signal from timer 0 will be selected to generate the basic clock SIOCLK Receiving Counter The receiving counter is a 4 bit binary counter used in asynchronous communicatio...

Page 129: ...of the receiving buffer 2 and SC0CR RB8 SC1CR RB8 are still preserved The parity bit added in 8 bit UART mode and the most significant bit MSB in 9 bit UART mode are stored in SC0CR RB8 SC1CR RB8 When in 9 bit UART mode the wake up function of the slave controllers is enabled by setting SC0MOD WU SC1MOD WU to 1 and interrupt INTRX0 INTRX1 occurs only when SC0CR RB8 SC1CR RB8 is set to 1 Transmissi...

Page 130: ...erated requests the next send data to the CPU Though there is no RTS pin a hand shake function can be easily configured by setting any port assigned to the RTS func tion The RTS should be output High to request data send halt after data receive is completed by a software in the RXD interrupt routine Figure 3 11 15 Handshake Function Note 1 If the CTS signal falls during transmission the next data ...

Page 131: ...smit and receive data with parity However parity can be added only in 7 bit UART or 8 bit UART mode With SC0CR EVEN SC1CR EVEN register even odd parity can be selected For transmission parity is automatically generated according to the data written in the transmission buffer SCBUF and data are transmitted after being stored in SC0BUF TB7 SC1BUF TB7 when in 7 bit UART mode while in SCMOD TB8 SCMOD ...

Page 132: ...at is immediately after last SCLK See Figure 3 11 21 SCLK input mode Timing used to transfer received data to data receive buffer 2 SC1BUF that is immediately after SCLK See Figure 3 11 22 3 11 3 Operational Description 1 Mode 0 I O interface mode This mode is used to increase the number of I O pins for trans mitting or receiving data to or from the external shifter register This mode includes SCL...

Page 133: ...ut INTES1 ITX1C will be set to generate INTTX1 interrupt Figure 3 11 20 Transmitting Operation in I O Interface Mode SCLK Input Mode Figure 3 11 19 Transmitting Operation in I O Interface Mode SCLK Output Mode When all data are output INTES1 ITXIC will be set to generate INTTX1 interrupt In SCLK output mode 8 bit data are output from TxD1 pin when SCLK input becomes active while data are written i...

Page 134: ... INTRX1 interrupt Figure 3 11 21 Receiving Operation in I O Interface Mode SCLK Output Mode In SCLK input mode the data is shifted in the receiving buffer 1 when SCLK input becomes active while the receive interrupt flag INTES1 IRX1C is cleared by read ing the received data When 8 bit data is received the data will be shifted in the receiving buffer 2 SC1BUF at the timing shown below and INTES1 IR...

Page 135: ... parity bit can be enabled or disabled by serial channel control register SC0CR PE SC1CR PE and even parity or odd parity is selected by SC0CR EVEN SC1CR EVEN when PE is set to 1 enable Setting example When transmitting data with the following format the control registers should be set as described below Channel 0 is explained here Select P90 as the TxD pin 3 Mode 2 8 bit UART Mode The 8 bit UART ...

Page 136: ... SC0BUF Read the received data Check for error 4 Mode 3 9 bit UART Mode The 9 bit UART mode can be specified by setting SC0MOD SM1 0 SC1MOD SM1 0 to 11 In this mode parity bit cannot be added For transmission the MSB 9th bit is written in SCM0D TB8 while in receiving it is stored in SCCR RB8 For writing and reading the buffer the MSB is read or written first then SC0BUF SC1BUF Wake up function In ...

Page 137: ...e and clears WU bit to 0 if the above select code matches its own select code The master controller transmits data to the specified slave controller whose SC0MOD WU SC1MOD WU bit is cleared to 0 The MSB bit 8 TB8 is cleared to 0 The other slave controllers with the WU bit remain ing at 1 ignore the receiving data because their MSBs bit 8 or RB8 are set to 0 to disable the interrupt INTRX0 INTRX1 T...

Page 138: ...evel 4 Enable INTRX0 and sets the interrupt level 5 SC0MOD 1 0 1 0 1 1 1 0 Set φ1 fc 2 as the transmission clock in 9 bit UART mode SC0BUF 0 0 0 0 0 0 0 1 Set the select code for slave controller 1 INTTX0 interrupt SC0MOD 0 Set TB8 to 0 SC0BUF Set data for transmission Main setting P9CR x x 0 1 P9FC x x x x x 1 ODE x x x x x x 1 INTES0 1 1 0 1 1 1 1 0 Enable INTRX0 and INTTX0 SC0MOD 0 0 1 1 1 1 1 ...

Page 139: ...ssive approximation Figure 3 12 1 shows the block diagram of the A D con verter The 4 channel analog input pins AN3 to AN0 are shared by input only P5 and so can be used as input port Figure 3 12 1 Block Diagram of A D Converter Note This A D converter does not have a built in sample and hold circuit Therefore when A D converting high frequency signals connect a sample and hold circuit externally ...

Page 140: ...140 TOSHIBA CORPORATION TMP96C141AF Figure 3 12 2 A D Control Register ...

Page 141: ...DR06 ADR05 ADR04 ADR03 ADR02 Read Write R After reset Undefined Function Upper 8 bits of A D result for AN0 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR11 ADR10 Read Write R After reset Undefined 1 1 1 1 1 1 Function Lower 2 bits of A D result for AN1 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12 Read Write R After reset Undefined Function Upper 8 bits of A D r...

Page 142: ...DR26 ADR25 ADR24 ADR23 ADR22 Read Write R After reset Undefined Function Upper 8 bits of A D result for AN2 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR31 ADR30 Read Write R After reset Undefined 1 1 1 1 1 1 Function Lower 2 bits of A D result for AN3 are stored 7 6 5 4 3 2 1 0 bit Symbol ADR39 ADR38 ADR37 ADR36 ADR35 ADR34 ADR33 ADR32 Read Write R After reset Undefined Function Upper 8 bits of A D r...

Page 143: ...can repeat mode scanning from AN0 AN3 is executed repeatedly A D conversion mode is selected by ADMOD REPET SCAN 5 A D Conversion Speed Selection There are two A D conversion speed modes high speed mode and low speed mode The selection is executed by ADMOD ADCS register When reset ADMOD ADCS will be initialized to 0 so that high speed conversion mode will be selected 6 A D Conversion End and Inter...

Page 144: ...epeat mode INTE0AD 1 0 0 Disable INTAD ADMOD x x 1 1 0 1 1 0 Start the A D conversion of analog input channels AN0 AN2 in the high speed scan repeat mode 3 13 Watchdog Timer Runaway Detecting Timer The TMP96C141AF is containing watchdog timer of Runaway detecting The watchdog timer WDT is used to return the CPU to the normal state when it detects that the CPU has started to malfunction runaway due...

Page 145: ...TOSHIBA CORPORATION 145 TMP96C141AF 3 13 1 Configuration Figure 3 13 1 shows the block diagram of the watchdog timer WDT Figure 3 13 1 Block Diagram of Watchdog Timer ...

Page 146: ...the watchdog timer out pin WDTOUT outputs 0 due to a watchdog timer overflow the peripheral devices can Figure 3 13 2 Normal Mode Figure 3 13 3 Reset Mode be reset The watchdog timer out pin is set to 1 by clearing the watchdog timer by writing a clear code 4EH in the WDCR reg ister In other words the WDTOUT keeps outputting 0 until the clear code is written The watchdog timer out pin can also be ...

Page 147: ...ontrol register WDCR This makes it difficult for the watchdog timer to be disabled by runaway However it is possible to return from the disable state to enable state by merely setting WDTE to 1 Watchdog timer out reset connection RESCR This register is used to connect the output of the watchdog timer with RESET terminal internally Since WDMOD RESCR is initialized to 0 at reset a reset by the watch...

Page 148: ...148 TOSHIBA CORPORATION TMP96C141AF Figure 3 13 4 Watchdog Timer Mode Register ...

Page 149: ...TOSHIBA CORPORATION 149 TMP96C141AF Figure 3 13 5 Watchdog Timer Control Register ...

Page 150: ...t pin to peripheral devices resets a CPU malfunction can also be acknowledged to other devices The watchdog timer restarts operation immediately after resetting is released The watchdog timer stops its operation in the IDLE and STOP modes In the RUN mode the watchdog timer is enabled However the function can be disabled when entering the RUN mode Example Clear the binary counter Set the watchdog t...

Page 151: ... 0 3 V V IL4 X1 0 3 0 2Vcc V V IH Input High Voltage AD0 15 2 2 Vcc 0 3 V V IH1 P2 P3 P4 P5 P6 P7 P8 P9 0 7Vcc Vcc 0 3 V V IH2 RESET NMI INTO P87 0 75Vcc Vcc 0 3 V V IH3 EA Vcc 0 3 Vcc 0 3 V V IH4 X1 0 8Vcc Vcc 0 3 V V OL Output Low Voltage 0 45 V I OL 1 6mA V OH Output High Voltage 2 4 V I OH 400µA V OH1 0 75Vcc V I OH 100µA V OH2 0 9Vcc V I OH 20µA I DAR Darlington Drive Current 8 Output Pins ma...

Page 152: ... A0 23 Valid D0 15 input 3 5x 65 154 110 ns 15 tRD RD fall D0 15 input 2 0x 50 75 50 ns 16 tRR RD Low width 2 0x 40 85 0 60 0 ns 17 tHR RD rise D0 15 Hold 0 0 0 0 0 ns 18 tRAE RD rise A0 15 output x 15 48 0 35 0 ns 19 tWW WR Low width 2 0x 40 85 0 60 0 ns 20 tDW D0 15 Valid WR rise 2 0x 50 75 0 50 0 ns 21 tWD WR rise D0 15 Hold 0 5x 10 21 0 15 0 ns 22 tAEH A0 23 Valid WAIT input 1WAIT n mode 3 5x ...

Page 153: ...TOSHIBA CORPORATION 153 TMP96C141AF 1 Read Cycle ...

Page 154: ...154 TOSHIBA CORPORATION TMP96C141AF 2 Write Cycle ...

Page 155: ...tSCY SCLK cycle 16x 1 0 8 µs tOSS Output Data rising edge of SCLK tSCY 2 5x 50 137 100 ns tOHS SCLK rising edge output data hold 5x 100 212 150 ns tHSR SCLK rising edge input data hold 0 0 0 ns tSRD SCLK rising edge effective data input tSCY 5x 100 587 450 ns 2 SCLK Output Mode Symbol Parameter Variable 16MHz 20MHz Unit Min Max Min Max Min Max tSCY SCLK cycle programmable 16x 8192x 1 512 0 8 409 6...

Page 156: ...mbol Parameter Variable 16MHz 20MHz Unit Min Max Min Max Min Max tINTAL NMI INT0 Low level pulse width 4x 250 200 ns tINTAH NMI INT0 High level pulse width 4x 250 200 ns tINTBL INT4 INT7 Low level pulse width 8x 100 600 500 ns tINTBH INT4 INT7 High level pulse width 8x 100 600 500 ns ...

Page 157: ...TOSHIBA CORPORATION 157 TMP96C141AF 4 8 Timing Chart for I O Interface Mode ...

Page 158: ... released by the external capacitance Therefore to fix the signal level by an external resistance under the bus is releasing the design must be carefully because of the level fix will be delayed The internal programmable pull up pull down resistance is switched active by the internal signal Symbol Parameter Variable 16MHz 20MHz Unit Min Max Min Max Min Max tBRC BUSRQ setup time for CLK 120 120 120...

Page 159: ...TOSHIBA CORPORATION 159 TMP96C141AF 4 10 Interrupt Operation Vcc 5V Ta 25 C unless otherwise noted ...

Page 160: ...SFRs include the I O ports and peripheral control registers allocated to the 128 byte addresses from 000000H to 00007FH 1 I O port 2 I O port control 3 Timer control 4 Pattern Generator control 5 Watch Dog Timer control 6 Serial Channel control 7 A D converter control 8 Interrupt control 9 Chip Select Wait Control Configuration of the table ...

Page 161: ...1CS AH P3CR 2AH PFFCR 4AH 6AH B2CS BH P3FC 2BH 4BH 6BH CH P4 2CH 4CH PG0REG 6CH DH P5 2DH 4DH PG1REG 6DH EH P4CR 2EH 4EH PG01CR 6EH FH 2FH 4FH 6FH 10H P4FC 30H TREG4L 50H SC0BUF 70H INTE0AD 11H 31H TREG4H 51H SC0CR 71H INTE45 12H P6 32H TREG5L 52H SC0MOD 72H INTE67 13H P7 33H TREG5H 53H BR0CR 73H INTET10 14H P6CR 34H CAP1L 54H SC1BUF 74H INTEPW10 15H P7CR 35H CAP1H 55H SC1CR 75H INTET54 16H P6FC 3...

Page 162: ... ORCF XORCF Instruction Symbol Name Address 7 6 5 4 3 2 1 0 P0 PORT0 00H P07 P06 P05 P04 P03 P02 P01 P00 R W Input mode Undefined P1 PORT1 01H P17 P16 P15 P14 P13 P12 P11 P10 R W Input mode 0 0 0 0 0 0 0 0 P2 PORT2 06H P27 P26 P25 P24 P23 P22 P21 P20 R W Input mode 0 0 0 0 0 0 0 0 P3 PORT3 07H P37 P36 P35 P34 P33 P32 P31 P30 R W Input mode Output mode 1 1 1 1 1 1 1 1 P4 PORT4 0CH P42 P41 P40 R W I...

Page 163: ...T1 Function 05H Prohibit RMW P27F P26F P25F P24F P23F P22F P21F P20F W 0 0 0 0 0 0 0 0 P1FC P1CR 00 IN 01 OUT 10 AD15 8 11 A23 16 P2CR PORT2 Control 08H Prohibit RMW P27C P26C P25C P24C P23C P22C P21C P20C W 0 0 0 0 0 0 0 0 Refer to the P2FC P2FC PORT2 Function 09H Prohibit RMW P27F P26F P25F P24F P23F P22F P21F P20F W 0 0 0 0 0 0 0 0 P2FC P2CR 00 IN 01 OUT 10 A7 0 11 A23 16 P3CR PORT3 Control 0AH...

Page 164: ... 0 0 0 PORT 1 PG1 OUT 0 PORT 1 PGO OUT P7FC PORT7 Function 17H Prohibit RMW P73F P72F P71F W 0 0 0 0 PORT 1 TO3 0 PORT 1 TO2 0 PORT 1 TO1 P8CR PORT8 Control 1AH Prohibit RMW P87C P86C P85C P84C P83C P82C P81C P80C W 0 0 0 0 0 0 0 0 0 IN 1 OUT P9CR PORT9 Control 1BH Prohibit RMW P95C P94C P93C P92C P91C P90C W 0 0 0 0 0 0 0 IN 1 OUT P8FC PORT8 Function 1CH Prohibit RMW P86F P83F P82F W W W 0 0 0 0 ...

Page 165: ...F1IS R W W R W 0 0 0 0 0 1 Double Buffer Enable 00 Invert TFF1 01 Set TFF1 10 Clear TFF1 11 Don t care 1 TFF1 Invert Enable 0 Inverted by Timer 0 TREG2 PWM Timer Register 2 26H R W Can read double buffer values Undefined TREG3 PWM Timer Register 3 27H R W Can read double buffer values Undefined P0MOD PWM0 MODE 28H Prohibit RMW FF2RD DB2EN PWM0INT PWM0M T2CLK1 T2CLK0 PWM0S1 PWM0S0 R W 0 0 0 0 0 0 0...

Page 166: ...set if overflowed TREG4L 16 bit Timer Register 4L 30H Prohibit RMW W Undefined TREG4H 16 bit Timer Register 4H 31H Prohibit RMW W Undefined TREG5L 16 bit Timer Register 5L 32H Prohibit RMW W Undefined TREG5H 16 bit Timer Register 5H 33H Prohibit RMW W Undefined CAP1L Capture Register 1L 34H R Undefined CAP1H Capture Register 1H 35H R Undefined CAP2L Capture Register 2L 36H R Undefined CAP2H Captur...

Page 167: ... 0 1 1 Timer 4 1 Double Buffer Enable TREG6L 16bit Timer Register 6L 40H Prohibit RMW W Undefined TREG6H 16bit Timer Register 6H 41H Prohibit RMW W Undefined TREG7L 16bit Timer Register 7L 42H Prohibit RMW W Undefined TREG7H 16bit Timer Register 7H 43H Prohibit RMW W Undefined CAP3L Capture Register 3L 44H R Undefined CAP3H Capture Register 3H 45H R Undefined CAP4L Capture Register 4L 46H R Undefi...

Page 168: ... PAT0 CCW0 PG0M PG0TE R W 0 0 0 0 0 0 0 0 0 8bit write 1 4bit write 0 Normal Rotation 1 Reverse Rotation 0 4bit Step 1 8bit Step PG1 trigger input enable 1 Enable 0 8bit write 1 4bit write 0 Normal Rotation 1 Reverse Rotation 0 4bit Step 1 8bit Step PG0 trigger input enable 1 Enable Symbol Name Address 7 6 5 4 3 2 1 0 WD MOD Watch Dog Timer Mode 5CH WDTE WDTP1 WDTP0 WARM HALTM1 HALTM0 RESCR DRVE R...

Page 169: ...d rate generator 10 Internal clock φ1 11 Don t care BR0CR Baud Rate Control 53H BR0CK1 BR0CK0 BR053 BR052 BR051 BR050 R W R W 0 0 0 0 0 0 0 Fix at 0 00 φt0 fc 4 01 φt2 fc 16 10 φt8 fc 64 11 φt32 fc 256 Set frequency divisor 0 F 1 prohibited SC1BUF Serial Channel 1 Buffer 54H RB7 TB7 RB6 TB6 RB5 TB5 RB4 TB4 RB3 TB3 RB2 TB2 RB1 TB1 RB0 TB0 R Receiving W Transmission Undefined SC1CR Serial Channel 1 ...

Page 170: ...R W 0 0 0 0 0 0 0 0 1 End 1 Busy 1 Repeat mode 1 Scan mode 1 Slow mode 1 START Analog Input Channel Series 1 AD REG0L AD Result Reg 0 low 60H ADR01 ADR00 R Undefined 1 1 1 1 1 1 AD REG0H AD Result Reg 0 high 61H ADR09 ADR08 ADR07 ADR06 ADR05 ADR04 ADR03 ADR02 R Undefined 1 AD REG1L AD Result Reg 1 low 62H ADR11 ADR10 R Undefined 1 1 1 1 1 1 AD REG1H AD Result Reg 1 high 63H ADR19 ADR18 ADR17 ADR16...

Page 171: ...TOSHIBA CORPORATION 171 TMP96C141AF 8 Interrupt Control 1 2 ...

Page 172: ...MA1 start vector DMA01V8 DMA1V7 DMA1V6 DAM1V5 DMA1V4 W 0 0 0 0 0 DMA2V DMA 2 request Vector 7EH Prohibit RMW µDMA2 start vector DMA2V8 DMA2V7 DMA2V6 DAM2V5 DMA2V4 W 0 0 0 0 0 DMA3V DMA 3 request Vector 7FH Prohibit RMW µDMA3 start vector DMA3V8 DMA3V7 DMA3V6 DAM3V5 DMA3V4 W 0 0 0 0 0 IIMC Interrupt Input Mode Control 7BH Prohibit RMW I0IE I0LE NMIREE W W W 0 0 0 1 INT0 input enable 0 INTO edge mod...

Page 173: ...M only 0 CS0 1 CAS0 0 16bit Bus 1 8bit Bus 00 2WAIT 01 1WAIT 10 1WAIT n 11 0WAIT 00 7F00H 7FFFH 01 400000H 10 800000H 11 C00000H B1CS Block 1 CS WAIT control register 69H Prohibit RMW B1E B1SYS B1CAS B1BUS B1W1 B1W0 B1C1 B1C0 W W W W W W W W 0 0 0 0 0 0 0 0 1 CS Enable 1 SYSTEM only 0 CS1 1 CAS1 0 16bit Bus 1 8bit Bus 00 2WAIT 01 1WAIT 10 1WAIT n 11 0WAIT 00 480H 7FFFH 01 400000H 10 800000H 11 C00...

Page 174: ...cated signal is described below STOP This signal becomes active 1 when the hold mode setting register is set to the STOP mode and the CPU executes the HALT instruction When the drive enable bit DRIVE is set to 1 however STP remains at 0 The input protection resistor ranges from several tens of ohms to several hundreds of ohms PO AD0 AD7 P1 AD8 15 A8 15 P2 A2 23 A0 7 P30 RD P31 WR P32 37 P40 41 P6 ...

Page 175: ...TOSHIBA CORPORATION 175 TMP96C141AF P42 CS2 CAS2 P5 AN0 3 P87 INT0 P90 TXD0 P93 TXD1 ...

Page 176: ...176 TOSHIBA CORPORATION TMP96C141AF NMI WDTOUT CLK EA AM8 16 ALE RESET ...

Page 177: ...TOSHIBA CORPORATION 177 TMP96C141AF X1 X2 VREF AGND ...

Page 178: ...ing request to outputting the system clock High Speed µDMA DRAM refresh mode When the bus is released BUSAK 0 for waiting to accept the interrupt DRAM refresh is not performed because of the high speed µDMA is generated by an interrupt Programmable Pull Up Down Resistance The programmable pull up down resistors can be selected ON OFF by program when they are used as the input ports The case of the...

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