Toshiba TLCS-900 Series, Manual

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16
TOSHIBA CORPORATION
TMP96C141AF
<Usage of read only mode (DRAM refresh)>
When the hardware configuration is as follows:
DRAM mapping size: = 1MB
DRAM data bus size: = 8 bits
DRAM mapping address range: = 100000H to
1FFFFFH
Set the following registers first; refresh is performed
automatically.
➀
Register initial value setting
LD XIX, 100000H
LDC DMAS0,XIX
…
mapping start address
LD A, 00001010B
LDC DMAM0, A
…
read only mode (for
DRAM refresh)
➁
Timer Setting
Set the timers so that interrupts are generated at
intervals of 62.5
µ
s or less.
➂
Interrupt controller setting
Set the timer interrupt mask h other interrupt mask.
Write the above timer interrupt vector value in the
High-Speed
µ
DMA start vector register, DMA0V.
(Operation description)
The DRAM data bus is an 8-bit bus and the micro
DMA is in read-only mode (4 bytes), so refresh is per-
formed four times per interrupt.
When a 512 refresh/8ms DRAM is connected, DRAM
refresh is performed sufficiently if the micro DMA is
started every 15.625
µ
s x 4 = 62.4
µ
s or less, since the
timing is 15.625
µ
s/refresh.
(Overhead)
Each processing time by the micro DMA is 1.8
µ
s (18
states) @ 20MHz with an 8-bit data bus.
In the above example, the micro DMA is started every
62.5
µ
s, 1.8
µ
s/62.5
µ
s = 0.029; thus, the overhead is
2.9%.
3.3.3 Interrupt Controller
Figure 3.3.3 (1) is a block diagram of the interrupt circuits. The
left half of the diagram shows the interrupt controller; the right
half includes the CPU interrupt request signal circuit and the
HALT release signal circuit.
Each interrupt channel (total of 20 channels) in the inter-
rupt controller has an interrupt request flip-flop, interrupt prior-
ity setting register, and a register for storing the high-speed
micro DMA start vector. The interrupt request flip-flop is used
to latch interrupt requests from peripheral devices. The flip-flop
is cleared to 0 at reset, when the CPU reads the interrupt
channel vector after the acceptance of interrupt, or when the
CPU executes an instruction that clears the interrupt of that
channel (writes 0 in the clear bit of the interrupt priority setting
register).
For example, to clear the INT0 interrupt request, set the
register after the as follows.
INTE0AD
←
---- 0 --- Zero-clears the INT0 Flip-Flop.
The status of the interrupt request flip-flop is detected by
reading the clear bit. Detects whether there is an interrupt
request for an interrupt channel.
The interrupt priority can be set by writing the priority in
the interrupt priority setting register (e.g., INTE0AD, INTE45,
etc.) provided for each interrupt source. Interrupt levels to be
set are from 1 to 6. Writing 0 or 7 as the interrupt priority dis-
ables the corresponding interrupt request. The priority of the
non-maskable interrupt (NMI pin, watchdog timer, etc.) is fixed
to 7. If interrupt requests with the same interrupt level are gen-
erated simultaneously, interrupts are accepted in accordance
with the default priority (the smaller the vector value, the higher
the priority).
The interrupt controller sends the interrupt request with
the highest priority among the simultaneous interrupts and its
vector address to the CPU. The CPU compares the priority
value <IFF2 to 0> set in the Status Register by the interrupt
request signal with the priority value sent; if the latter is higher,
the interrupt is accepted. Then the CPU sets a value higher
than the priority value by 1 in the CPU SR<IFF2 to 0>. Interrupt
requests where the priority value equals or is higher than the
set value are accepted simultaneously during the previous
interrupt routine. When interrupt processing is completed (after
execution of the RETI instruction), the CPU restores the priority
value saved in the stack before the interrupt was generated to
the CPU SR<IFF2 to 0>.
The interrupt controller also has four registers used to
store the high-speed micro other DMA start vector. These are I/
O registers; unlike other DMA registers (DMAS, DMAD, DMAM,
and DMAC), they can be accessed in either normal or system
mode. Writing the start vector of the interrupt source for the
micro DMA processing (see Table 3.3 (1)), enables the corre-
sponding interrupt to be processed by micro DMA processing.
The values must be set in the micro DMA parameter registers
(e.g., DMAS and DMAD) prior to the micro DMA processing.
DI instruction