Toshiba SD-1300A, Service Manual

Page: 69 / 93

3-27
Table 3-5-5 ZR36732 (3/5)
Pin
No.
111
100
127
92
95
93
96
131
133
136
|
138
113
139
141
151
149
148
152
|
159
150
147
Function
Apply reference voltage for DAC gain
adjustment.
Composite sync output. Only when RGB
analog output is selected, the pin takes
effective. For other case, the pin is fixed to
Low.
Main video clock input or output. 27.000
MHz.
Two-divided VCLKx2 signal. The signal is
used as data and sync signal qualifier.
Horizontal sync bidirectional signal pin. The
polarity and length are programmable.
Vertical sync bidirectional signal pin. The
polarity and length are programmable.
Field identification bidirectional signal pin.
The polarity is programmable.
Audio master clock input/output. The
sampling frequency can be selected
among 384fs, 256fs, 192fs and 128fs.
(programmable)
S/PDIF transmitter output. Available to
connect to DAC as the 4th audio output
(AOUT[3]). After reset, the pin develops
low level signal.
PCM stereo audio serial output for DAC.
After reset, the pin develops low level
signal.
PCM stereo audio serial input for ADC.
AOUT [4:0] and LR clock output of AIN.
The square waveform appears in the
sampling frequency.
The polarity of LR is programmable.
AOUT [4:0] and bit clock output of AIN.
AOUT is developed at the rising and falling
edges of the clock signal and AIN is
latched.
DVD-DSP data request output (polarity
programmable).
DVD-DSP data effective input (polarity
programmable).
DVD-DSP data sector start input (polarity
programmable).
DVD-DSP data input bus.
DVD-DSP data bit strobe (clock) input.
Polarity programmable.
DVD-DSP error input. Polarity
programmable.
Name
VREF
COSYNC
VCLKx2
VCLK
HSYNC
VSYNC
FI
AMCLK
S/PDIF
(AOUT[3])
AOUT[2:0]
AIN
ALRCLK
ABCLK
DVDREQ
DVDVALID
DVDSOS
DVDDAT
[7:0]
DVDSTRB
DVDERR
Digital video port (5 pins)
Digital audio port (8 pins)
Table 3-5-5 ZR36732 (4/5)
Function
SDRAM bidirectional data bus.
SDRAM address bus output.
SDRAM row selection (active: low) output.
SDRAM column selection (active: low)
output.
SDRAM clock output (same as internal
process clock).
SDRAM data masking (active: high) output.
SDRAM chip select (active: low) output.
Lower 2 Mbyte device.
SDRAM chip select (active: low) output.
Upper 2 Mbyte device.
SDRAM write enable (active: low) output.
Test pin. Connect to GNDP in normal use.
Test pin. Connect to GNDP in normal use.
Test pint Connect to VDDP in normal use.
GND for 3.3V digital power supply.
3.3V digital power supply.
Name
RAMDAT
[15:0]
RAMADD
[11:0]
RAMRAS#
RAMCAS#
PCLK
RAMDQM
RAMCS0#
RAMCS1#
RAMWE#
SCNENBL
TESTMODE
ICEMODE
GNDP
VDDP
DVD-DSP interface (13 pins)
TEST signal (3 pins).
SDRAM interface (35 pins)
Power supply signal (49 pins).
Pin
No.
68,
70,
72,
74
|
76,
78,
79,
81,
82,
84,
85,
87,
88,
90,
91
41,
42,
43,
45
|
48,
50,
51,
53
|
55
60
61
66
64
57
59
62
125
129
112
10,
40,
49,
56,
65,
69,
80,
86,
97,
128,
146
3,
16,
26,
38,
44,
52,
58,
67,
71,
77,
83,
89,
94,
98,
126,
135,
140