Toshiba SD-1300A, Service Manual

Page: 68 / 93

3-26
Table 3-5-5 ZR36732 (1/5)
Pin
No.
124
122
160
2
1
4
20
|
25,
17,
18
9,
11,
13,
15
8
7
6
5
27
|
30
32
31
34
Function
Reset input (active: low). Initializing
process of the device will start when
deasserting is performed after asserting.
Standby input (active: low). When asserting
in accordance with RESET#, all the output
pins and bidirectional pins enter the float
state, and the device is electrically cut off.
All internal operations stop and the power
consumption can be minimized. At standby,
contents of SDRAM and setup parameters
are not preserved.
Display output of Idle, Init or Reset state
(active high). After reset, the device enters
the active state.
Determines the data bus width of host
interface. Only during reset, modification
will be available. At low level (GNDP), the
host interface of the device is set to 2 or 8
bit width, at high level (VDDP) is set to 16
bit width.
Determines the bite order of host interface
data bus at 16 bit width (HWID is VDDP).
Only during reset, modification will be
available. Sets the device so that m.s. bite
is entered/developed by HD [15:8] at low
level (GNDP), and m.s. bite is done by HD
[7:0] at high level (VDDP).
Connects to GNDP when HWID is at GND
level.
Determines protocol of the host bus. Only
during reset, modification will be available.
Sets the device to type A at low level
(GNDP) and type B at high level (VDDP).
8 l.s of the host data bus. When connecting
HWID input to GNDP, only the 8 l.s. signal
is defined as a host data signal. When
connecting HWID to VDDP, the connection
is used as a 8 l.s. line of 16 bit data bus.
When connecting HWID to VDDP, the
connection is used as 11:8 data line of 16
bit host data bus.
When connecting HWID to VDDP, the
connection is used as 15:12 data line of 16
bit host data bus. When connecting HWID
to GNDP, the connection is used as CD-
DSP serial input port pin as defined below.
CD-DSP bit clock input.
CD-DSP data input.
CD-DSP LR clock (Frame) input.
CD-DSP data error input.
Host address input. Inputs address signal
which specifies the physical address of the
device.
Host chip select input. Active: low.
Host protocol type A (HTYPE=GNDP): HR/
W#. The input to determine the direction of
host access.
Host protocol type B (HTYPE=VDDP):
HWR#. Host write input (Active: low).
Host protocol type A (HTYPE=GNDP):
HDS#. Data strobe input (Active: low).
Host protocol type B (HTYPE=VDDP):
HRD#. Host read in input (Active: low).
Name
RESET#
STDBY#
IDLE
HWID
HORD
HTYPE
HD[7:0]
(HD[7:4])
(HD[3])
(HD[2:1])
(HD[0])
HD[11:8]
(HD[11])
(HD[10:8])
HD[15:12]
CDCLK
(HD[12])
CDDAT
(HD[13])
CDFRM
(HD[14])
CDERR
(HD[15])
HA[3:0]
HCS#
HWR# (HR/
W#)
HRD#
(HDS#)
Host interface, CD-DSP interface, sub code interface (32 pins)
Table 3-5-5 ZR36732 (2/5)
Pin
No.
36
37
39
134
145
143
120
117
119
118
115
102
105
106
103
108
Function
Host ready output (active: high). When
transmitting a stream through host bus with
this signal, use the signal. And an external
pull up resistor is required.
Confirm the signal becomes active before
transmitting every packet signal, 1 packet
signal is CodBurstLen byte length
transmission signal. After that, it is
available to write the bit stream signals up
to the CodBurstLen byte to the device
continuously.
Interrupt request (active: low). Deasserted
by host reading the interrupt status resistor
of the device. And also deasserted either
after host masks the interruption with the
interrupt mask resistor of the device or
after reset.
When HIRQ# is not asserted, 3-state
status starts. (External pull up resistor is
required.)
Host aknowledge output (active: Low).
When the type A protocol is used, the
device asserts the output and informs the
completion of read/write cycle.
When the signal is not active, 3-state
status starts. (External pull up resistor is
required.)
When the type B protocol is used, the
signal works as a Wait output signal. When
using a host with high speed
(microprocessor), the signal connection is
not always required.
General bidirectional pin to watch/control
by ADP micro code. After reset, the pin is
defined to use for input. By the ADP
command, setting is available.
General input to be watched by DVP micro
code.
General output to be controlled by DVP
micro code. After reset, the pin develops
Low.
27.000 MHz clock or X’tal input for main
processor.
27.000 MHz master clock input for audio.
In standard use, the pin should be
connected to GCLK.
Output to X’tal connected to GCLK. When
not using X’tal for GCLK, XO is kept
unconnected.
PLL configuration input. During reset,
modification will be available. For general
use, both pins should be connected to
GNDP.
At CVBS, the composite video signal is
developed.
At RGB, G signal is developed.
At YUV, Y signal is developed.
At CVBS, Y signal is developed.
At RGB, R signal is developed.
At YUV, V signal is developed.
At CVBS, C signal is developed.
At RGB, B signal is developed.
At YUV, U signal is developed.
Develops either of CVBS or C signal.
Insert a resistor load for DAC gain
adjustment between GND and DAC.
Name
HRDY
HIRQ#
HACK#
GPIO
GPSI
GPSO
GCLK
GCLK1
XO
PLLCFG
[1:0]
CVBS/G/Y
(DAC A)
Y/R/V
(DAC B)
C/B/U
(DAC C)
CVBS/C
(DAC D)
RSET
GPI/O signal (3 pins)
Analog video port (7 pins)
PLL signal (5 pins)