3-25
Table 3-5-4 TMP94C251AF(Z) (4/5)
Pin
No.
24
25
26
131
|
138
3
4
126
127
128
129
125
117
|
124
28
42
30,
40
32,
33
31
38,
39
41
139
140
1
2
Function
Port F4: I/O port
Serial transmission data 1 (open drain
output is possible)
Port F5: I/O port
Serial reception data 1
Port F6: I/O port
Serial transmission is possible 1
Serial clock I/O 1
Port G: Input port
Analog input: Enters 10 bit AD converter
DA output 0: Develops 8 bit DA converter 0
DA output 1: Develops 8 bit DA converter 1
Port H0: I/O port
Terminal count 0: Develops “H” level with
strobe when micro DMA channel 0 counts
0.
Port H1: I/O port
Terminal count 1: Develops “H” level with
strobe when micro DMA channel 1 counts
0.
Port H2: I/O port
Terminal count 2: Develops “H” level with
strobe when micro DMA channel 2 counts
0.
Port H3: I/O port
Terminal count 3: Develops “H” level with
strobe when micro DMA channel 3 counts
0.
Port H4: I/O port (schmitt input)
Interrupt request terminal 0: Terminal for
interrupt request signal of which rising/
falling edge is programmable. (schmitt
input)
Port Z: I/O port
Non maskable interrupt request terminal:
Terminal for interrupt request signal at the
falling edge. Depending on the program,
interrupt request signal at rising edge may
be used. (schmitt input)
Watch dog timer output terminal
Address mode: Selects the starting
external data bus width after releasing the
reset
AM1 = “0”, AM0=”0”: starting at the 8 bit
external data bus
AM1 = “0”, AM0=”1”: starting at the 16 bit
external data bus
AM1 = “1”, AM0=”0”: Do not set.
AM1 = “1”, AM0=”1”: Do not set.
Test: Used to “GND”
Clock: Develops System clock
Oscillator connection terminal
Reset: Device is initialized.
(With the pull-up resistance) (schmitt input)
Reference voltage input terminal for 10 bit
AD converter (H)
Reference voltage input terminal for 10 bit
AD converter (L)
Reference voltage input terminal for 8 bit
DA converter (H)
Reference voltage input terminal for 8 bit
DA converter (L)
Name
PF4
TXD1
PF5
RXD1
PF6
CTS1
SCLK1
PG0~PG7
AN0~AN7
DAOUT0
DAOUT1
PH0
TC0
PH1
TC1
PH2
TC2
PH3
TC3
PH4
INT0
PZ0~PZ7
NMI
WDTOUT
AM0~1
TEST0~1
CLK
X1/X2
RESET
VREFH
VREFL
DAREFH
DAREFL
Table 3-5-4 TMP94C251AF(Z) (5/5)
Pin
No.
142
141
144
143
36
34
5,
27,
43,
61,
78,
88,
98,
116
14,
37,
54,
69,
87,
89,
107,
130
Function
10 bit AD converter power supply terminal
10 bit AD converter GND terminal (0V)
8 bit DA converter power supply terminal
8 bit DA converter GND terminal (0V)
Power supply terminal for clock doubler.
GND terminal for clock doubler.
Digital power supply terminal (+5V)
Digital GND terminal (0V)
Name
ADVCC
ADVSS
DAVCC
DAVSS
CLVCC
CLVSS
DVCC
DVSS
Summary of Contents for SD-1300A
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Page 57: ...Fig 3 4 5 4 3 3 Front Display Power Switch Block Diagram 3 9 3 10 ...
Page 58: ...m Fig 3 4 6 4 4 Main Block Diagrams 4 4 1 Servo System Block Diagram 3 11 3 12 ...
Page 59: ...Fig 3 4 7 4 4 2 Logical System Block Diagram 3 13 3 14 ...
Page 71: ...5 3 2 Main Circuit Diagram Fig 3 5 5 3 29 3 30 3 31 3 32 ...
Page 73: ...3 34 1 3 4 A B C D E G 2 5 F 5 4 Motor System Circuit Diagram Fig 3 5 7 ...
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Page 89: ...4 6 5 PARTS LIST ...
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